A novel low power hybrid cache using GC-EDRAM cells

In a typical embedded CPU, large on-chip storage is critical to meet high performance requirements. However, the fast increasing size of the on-chip storage based on traditional SRAM cells makes the area cost and energy consumption unsustainable for future embedded applications. Replacing SRAM with DRAM on the CPU’s chip is generally considered not worthwhile because DRAM is not compatible with the common CMOS logic and requires additional processing steps beyond what is required for CMOS. However a special DRAM technology, Gain-Cell embedded-DRAM (GC-eDRAM)  [1], [2], [3] is logic compatible and retains some of the good properties of DRAM (small and low power). In this paper we evaluate the performance of a novel hybrid cache memory where the data array, generally populated with SRAM cells, is replaced with GC-eDRAM cells while the tag array continues to use SRAM cells. Our evaluation of this cache demonstrates that, compared to the conventional SRAM-based designs, our novel architecture exhibits comparable performance with less energy consumption and smaller silicon area, enabling the sustainable on-chip storage scaling for future embedded CPUs.     

Autonomous system for data collection: Location and mapping issues in post-disaster environment

Disaster relief requires many resources. Depending on the circumstances of each event, it is important to rapidly choose the suitable means to respond to the emergency intervention. A brief review of the conditions and means demonstrated the usefulness of an autonomous stand-alone machine for these missions. If many techniques and technologies exist, their relevant combination to achieve such a system presents several challenges. This communication tries to outline the possible achievement of an autonomous vehicle under these particular circumstances. This paper focuses on the specific working conditions and welcomes future contributions from robotics and artificial intelligence.In the necessarily limited scope of this article, the authors focus on a particularly critical aspect: location. Indeed, this machine is intended to evolve in heterogeneous and dangerous environment and without any outside contacts that could last up to several days. This blackout, due to the propagation difficulties of electromagnetic waves in the ground, induces an independence of the localisation process and makes the use of any radio navigation support system (GNSS), most of the time, impossible. The knowledge of the position of the system, both for navigation of the autonomous system (Rover) and location of targets (victims buried under debris) must be able to be estimated without contributions from external systems. Inertial classical techniques, odometer, etc., have to be adapted to these conditions during a long period without external support. These techniques also have to take into account that energy optimisation requests the use of low-power processors. Consequently, only poor computing capacity is available on-board.The article starts with a presentation of the context of a post-disaster situation as well as the main missions of Search and Rescue (SaR). It is followed by the analysis of autonomous navigation located in a post-earthquake situation. We will then discuss means to determine the attitude of the autonomous system and its position. The interest of hybridisation with external systems – whenever possible –, will be evaluated with a view to correcting deviations suffered by the system during its mission. Finally, prospects and future work are presented.     

DSP--数字化时代的基因芯片

DSP是当今发展最为迅速的和最有发展前景的技术之一。与普通CPU和MCU相比 ,DSP在数字信号处理方面有着无可比拟的优势 ,特别适合网络、通信、控制等需要进行大量数字信号处理的应用场合。今天DSP已经成为通信、计算机、网络、工业控制以及家用电器等电子产品中不可或缺的基础器件 ,DSP在通信、计算机、网络、工业控制以及消费类电子产品等领域有着非常广泛的应用 ,本文阐述了DSP的特点、应用和市场以及DSP技术的发展前景。     

宽工作电压范围单电源CMOS误差放大器

采用0.8μm标准数字CMOS工艺(VTN0=0.836V,VTP0=0.930V),设计并流片验证了具有宽工作电压范围(3～6V),可作SOC系统动态电源管理芯片内部误差放大器应用的单电源CMOS运算放大器。该误差放大器芯核同时具有适合低电压工作,并对工艺参数变化不敏感的优点。对于相同的负载情况,在3V的工作电压下,开环电压增益AD=83.1dB,单位增益带宽GB=2.4MHz,相位裕量Φ=85.2°,电源抑制比PSRR=154.0dB,转换速率Sr=2.2V/μs;在6V工作电压下,AD=85.1dB,GB=2.4MHz,Φ=85.4°,PSRR=145.3dB,Sr=3.4V/μs。     

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs

Modular testing is an attractive approach to testing large system ICs, especially if they are built from pre-designed reusable embedded cores. This paper describes an automated modular test development approach. The basis of this approach is that a core or module test is dissected into a test protocol and a test pattern list. A test protocol describes in detail how to apply one test pattern to the core, while abstracting from the specific test pattern stimulus and response values. Subsequent automation tasks, such as the expansion from core-level tests to system-chip-level tests and test scheduling, all work on test protocols, thereby greatly reducing the amount of compute time and data involved. Finally, an SOC-level test is assembled from the expanded and scheduled test protocols and the (so far untouched) test patterns. This paper describes and formalizes the notion of test protocols and the algorithms for test protocol expansion and scheduling. A running example is featured throughout the paper. We also elaborate on the industrial usage of the concepts described.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.     

Effect of the polymer matrices on the dielectric behavior of a percolative high-k polymer composite for embedded capacitor applications

High dielectric constant (high-k) polymer composites are of great interest for embedded capacitor applications. Previously, we demonstrated that epoxy—aluminum composites are promising for embedded capacitor applications, because they have a high dielectric constant and a low dielectric loss due to the core—shell structure of the self-passivated aluminum particles. In this work, to further understand the dielectric behavior of aluminum composites, lower-loss polymers such as silicone, polyimide, polynorbornene, and benzocyclobutene were explored as matrices for the aluminum composites. It is found that the polymer matrices can significantly change the dielectric properties of the aluminum composites. A polymer matrix with a lower dielectric constant generally results in a lower dielectric constant of its aluminum composites. In this regard, polymer—aluminum composites have a similar dielectric characteristic as polymer—ceramic composites. Thermomechanical properties of aluminum composites were characterized by a thermomechanical analyzer.     

ROI-based Watermarking Scheme for JPEG 2000

A new region of interest (ROI)-based watermarking method for JPEG 2000 is presented. The watermark is embedded into the host image based on the characteristics of the ROI to protect rights to the images. This scheme integrates the watermarking process with JPEG 2000 compression procedures. Experimental results have demonstrated that the proposed watermark technique successfully survives JPEG 2000 compression, progressive transmission, and principal attacks.     

基于SOC的PAGER控制芯片设计

文章讨论了PAGER控制器芯片（ZQD021）的系统设计，该控制器内部集成了FLASH，SRAM，POCSAG协议解码器和嵌入式MCU CORE。重点分析了芯片的可测性设计（DFT），内嵌FLASH设计，低功耗设计，其设计方法和思路对消费类和嵌入式控制芯片的设计有一定的借鉴意义。     

Evolution of the structural stability of large Cu,Ni, Pd,and Ag clusters with size: An analysis within the embedded atom method

A study of the structural stability of clusters made up of a single component has been carried out within the Embedded Atom Method. Perfect icosahedral and cuboctahedral Cu, Ni, Pd, and Ag clusters with up to 5083 atoms have been compared. The icosahedron is found to be the stable structure for small clusters, and a change of structure from icosahedral to cuboctahedral is found as the cluster size increases. A contraction of the interatomic distances results when the cluster size decreases.