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一种针对AVS去块滤波的高性能结构   总被引:1,自引:0,他引:1  
在AVS视频解码器设计中,环路去块滤波成为实时处理的瓶颈之一。该文提出了一种实用的环路滤波结构,处理一个宏块只需要164个周期。使用新颖的滤波顺序,待滤波数据缓冲从1616宏块大小降低为168半宏块大小。使用数据重用策略, 滤波中间数据的存储空间大大减小。实验表明,使用0.18m CMOS工艺,在50MHz下综合,该文提出的设计只需要9.2k门。工作在50MHz频率下,该文提出的设计能够支持高清视频解码的实时滤波处理。  相似文献   
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Blocking artifact, characterized by visually noticeable changes in pixel values along block boundaries, is a common problem in block-based image/video compression, especially at low bitrate coding. Various post-processing techniques have been proposed to reduce blocking artifacts, but they usually introduce excessive blurring or ringing effects. This paper proposes a self-learning-based post-processing framework for image/video deblocking by properly formulating deblocking as an MCA (morphological component analysis)-based image decomposition problem via sparse representation. Without the need of any prior knowledge (e.g., the positions where blocking artifacts occur, the algorithm used for compression, or the characteristics of image to be processed) about the blocking artifacts to be removed, the proposed framework can automatically learn two dictionaries for decomposing an input decoded image into its “blocking component” and “non-blocking component.” More specifically, the proposed method first decomposes a frame into the low-frequency and high-frequency parts by applying BM3D (block-matching and 3D filtering) algorithm. The high-frequency part is then decomposed into a blocking component and a non-blocking component by performing dictionary learning and sparse coding based on MCA. As a result, the blocking component can be removed from the image/video frame successfully while preserving most original visual details. Experimental results demonstrate the efficacy of the proposed algorithm.  相似文献   
4.
In this paper, a high performance and low complexity loop filter is proposed for intra prediction coding. Although the deblocking loop filter (DLF) has achieved outstanding performance on suppressing quantization noise, it also induces details information loss because of the smoothing operation. To achieve better restoration performance, we propose a filter set named mode dependent loop filter (MDLF) which adaptively select the filter coefficients according to various local characteristics. In the homogeneous areas, the task of the filter emphasizes on smoothing the noise. In the heterogeneous areas, the proposed filter concentrates on preserving the details. Based on the spatial correlation assumption and statistical analysis, the intra mode combination is used to classify the training samples with different local characteristics. Then the classical least mean square error framework is employed to solve the coefficients for the proposed filter set. In this way, a more efficient adaptive loop filter scheme can be achieved for specific intra mode combination. Experiment results show that the proposed loop filter achieves superior coding gains compared to the H.264/AVC High Profile. Furthermore, relative to QALF+DLF, a comparable performance also can be achieved by the proposed MDLF with far less complexity increase.  相似文献   
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Exploiting specific properties of the algorithm, a high-throughput pipelined architecture is introduced to implement the H.264/AVC deblocking filter. The architecture was synthesized in 0.18 μm technology and the clock frequency and area are 400 MHz and 16.8 Kgates, respectively. Also, it is able to filter 217 and 55 Frames per second (Fps) for Full- and Ultra-HD videos, respectively. The introduced architecture outperforms similar ones in terms of frequency (1.8× up to 4×), throughput, (1.5× up to 3.8×), and Fps. Moreover, extensions to support different sample bit-depths and chroma formats are included. Also, experimental results for different FPGA families are offered.  相似文献   
6.
H.264编码环中的去块效应滤波系统   总被引:5,自引:1,他引:5  
陆亮  楼剑  虞露 《电视技术》2003,(7):12-14
介绍了H.264的编解码模型系统中的去块效应滤波系统,分析了该系统原理及其相对于以往去块效应滤波系统的改进。并通过仿真实验验证了该系统在提高图像质量和降低视频流码率上的较好作用。  相似文献   
7.
This paper presents a new edge‐protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge‐protection maps. Based on these maps, a two‐step adaptive filter which includes offset filtering and edge‐preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory‐reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 µm CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.  相似文献   
8.
Deblocking filter is one of the most time consuming modules in the H.264/AVC decoder as indicated in many studies. Therefore, accelerating deblocking filter is critical for improving the overall decoding performance. This paper proposes a novel parallel algorithm for H.264/AVC deblocking filter to speed the H.264/AVC decoder up. We exploit pixel-level data parallelism among filtering steps, and observe that results of each filtering step only affect a limited region of pixels. We call this “the limited propagation effect”. Based on this observation, the proposed algorithm could partition a frame into multiple independent rectangles with arbitrary granularity. The proposed parallel deblocking filter algorithm requires very little synchronization overhead, and provides good scalability. Experimental results show that applying the proposed parallelization method to a SIMD optimized sequential deblocking filter achieves up to 95.31% and 224.07% speedup on a two-core and four-core processor, respectively. We have also observed a significant speedup for H.264/AVC decoding, 21% and 34% on a two-core and four-core processor, respectively.
Ja-Ling WuEmail:

Sung-Wen Wang   received his Ph.D. degree in computer science from National Taiwan University, Taipei, Taiwan, in 2008. His general research interests are in the field of digital video coding, codec-processor architecture co-design and multimedia systems optimization, especially in video coding technology optimization. Shu-Sian Yang   received the B.S. and M.S. degrees in computer science and information engineering from National Taiwan University, Taiwan, in 2005 and 2007, respectively. His current research interests include video compression, image processing, and multimedia application. He is currently working at PixArt Imaging Inc., HsinChu, Taiwan as a senior engineer. Hong-Ming Chen   received the B.S. degree in computer science and information engineering from National Taiwan University, Taiwan, in 2007. He is currently pursuing the M.S. degree in the same department in National Taiwan University. His current research interests include video compression, image processing, digital content analysis, and multimedia application. Chia-Lin Yang   received the B.S. degree from the National Taiwan Normal University, Taiwan, R.O.C., in 1989, the M.S. degree from the University of Texas at Austin in 1992, and the Ph.D. degree from the Department of Computer Science, Duke University, Durham, NC, in 2001. In 1993, she joined VLSI Technology Inc. (now Philips Semiconductors) as a Software Engineer. She is currently an Associate Professor in the Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. Her research interests include energy-efficient microarchitectures, memory hierarchy design, and multimedia workload characterization. Dr. Yang is the recipient of a 2000-2001 Intel Foundation Graduate Fellowship Award and 2005 IBM Faculty Award. Ja-Ling Wu   (SM ’98, Fellow ’08) received his Ph.D. degree in electrical engineering from Tatung Institute of Technology, Taipei, Taiwan, in 1986. From 1986 to 1987, he was an Associate Professor of the Electrical Engineering Department, Tatung Institute of Technology. Since 1987, he transferred to the Department of Computer Science and Information Engineering(CSIE), National Taiwan University(NTU), Taipei, where he is presently a Professor. From 1996 to 1998, he was assigned to be the first Head of the CSIE Department, National Chi Nan University, Puli, Taiwan. During his sabbatical leave (from 1998 to 1999), Prof. Wu was invited to be the Chief Technology Officer of the Cyberlink Corp. In this one year term, he involved with the developments of some well-known audio-video softwares, such as the PowerDVD. Since Aug. 2004, Prof. Wu has been appointed to head the Graduate Institute of Networking and Multimedia, NTU. Prof. Wu has published more than 200 technique and conference papers. His research interests include digital signal processing, image and video compression, digital content analysis, multimedia systems, digital watermarking, and digital right management systems. Prof. Wu was the recipient of the Outstanding Young Medal of the Republic of China in 1987 and the Outstanding Research Award three times of the National Science Council, Republic of China, in 1998, 2000 and 2004, respectively. In 2001, his paper “Hidden Digital Watermark in Images” (co-authored with Prof. Chiou-Ting Hsu), published in IEEE Transactions on Image Processing, was selected to be one of the winners of the “Honoring Excellence in Taiwanese Research Award”, offered by ISI Thomson Scientific. Moreover, his paper “Tiling Slideshow” (co-authored with his students) won the Best Full Technical Paper Award in ACM Multimedia 2006. Professor Wu was selected to be one of the lifetime Distinguished Professors of NTU, November 2006. Prof. Wu has been elected to be IEEE Fellow, since 1 January 2008, for his contributions to image and video analysis, coding, digital watermarking, and rights management.   相似文献   
9.
In this paper, we propose a parallelization method for a High Efficiency Video Coding (HEVC) deblocking filter with transform unit (TU) split information. HEVC employs a deblocking filter to boost perceptual quality and coding efficiency. The deblocking filter was designed for data‐level parallelism. In this paper, we demonstrate a method of distributing equal workloads to all cores or threads by anticipating the deblocking filter complexity based on the coding unit depth and TU split information. We determined that the average time saving of our proposed deblocking filter parallelization method has a speed‐up factor that is 2% better than that of the uniformly distributed parallel deblocking filter, and 6% better than that of coding tree unit row distribution parallelism. In addition, we determined that the speed‐up factor of our proposed deblocking filter parallelization method, in terms of percentage run‐time, is up to 3.1 compared to the run‐time of the HEVC test model 12.0 deblocking filter with a sequential implementation.  相似文献   
10.
In order to improve the performance of fractal video coding, we explore a novel fractal video sequences codec with automatic region-based functionality. To increase the quality of decoding image, intra frame coding, deblocking loop filter and sub-pixel block matching are applied to the codec. An efficient searching algorithm is used to increase the compression ratio and encoding speed. Automatic region-based fractal video sequences coding reduces coding stream greatly. Experimental results indicate that the proposed algorithm is more robust, and provides much less encoding time and bitrate while maintaining the quality of decompression image than the conventional CPM/NCIM method and other related references. We compare the proposed algorithm with three algorithms in Refs. [24], [25], [26], and the results of all these four algorithms are compared with H.264. The bitrate of the proposed algorithm is decreased by 0.11% and the other algorithms are increased by 4.29%, 6.85% and 11.62%, respectively. The average PSNR degradations of the four algorithms are 0.71 dB, 0.48 dB, 0.48 dB and 0.75 dB. So the bitrate of the proposed algorithm is decreased and the other algorithms are increased. At the meantime the compression time is reduced greatly, about 79.19% on average. The results indicate that, on average, the proposed automatic region-based fractal video sequences coding system can save compression time 48.97% and bitrate 52.02% with some image quality degradation in comparison with H.264, since they are all above 32 dB and the human eyes are insensitive to the differences.  相似文献   
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