A novel low-latency DRAM based on the bitline-discharge rate

As well known by computer architects, the performance gap between the processor and the memory has been increasing over the years. This causes what is known as the memory wall. In order to alleviate the problem, a novel fast readout scheme is proposed in this article for the single-transistor single-capacitor dynamic random-access memory (1T-1C DRAM) cells. The proposed scheme works in the current domain in which the difference between the discharging rates of the bitline in the cases of ‘1’ and ‘0’ readings is detected. The proposed scheme is analysed quantitatively and compared with the conventional readout scheme. It is verified by simulation adopting the 45 nm CMOS Berkley predictive-technology model (BPTM) and shows 44 and 7.7% reductions in the average read-access and cycle times, respectively, as compared to the conventional readout scheme. It is also shown that the power is saved according to the proposed scheme if the probability of occurrence of ‘0’ storage exceeds 66.7%. This minimum value can be alleviated, however, at the expense of a smaller saving in the average read-access time. The impacts of process variations and technology scaling are also taken into account.     

A new approach to cell size scaling with a multi-dual cell and a buffer/background programming of unified RAM

New investigations are presented here on a high-density and DRAM-like high-speed non-volatile memory (NVM) application of unified RAM (URAM). For a high-density application of URAM, multiple data storage is demonstrated with a multi-dual cell (MDC). Because each NVM state can be split by programming with a one-transistor (1T) DRAM without a capacitor, the total number of memory states can be doubled. Furthermore, a high-speed DRAM-level NVM scheme is proposed for the joint operation of 1T DRAM buffer programming and NVM post-background programming. The MDC and the proposed scheme are unique URAM properties that can extend the application range of memory devices.     

一种基于碳纳米管的随机存储器

利用碳纳米管之间范德瓦耳斯力,设计了一种基于碳纳米管的可读写的随机存储器,研究了系统的双稳性,讨论了存储器的优点和可行性,并得出系统具有良好存储效应所应满足的条件 关键词： 碳纳米管 范德瓦耳斯力 动态随机存储器     

Fully Programmable Memory BIST for Commodity DRAMs

To accomplish a high‐speed test on low‐speed automatic test equipment (ATE), a new instruction‐based fully programmable memory built‐in self‐test (BIST) is proposed. The proposed memory BIST generates a high‐speed internal clock signal by multiplying an external low‐speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on‐the‐fly to perform complicated and hard‐to‐implement functions, such as loop operations and refresh‐interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.     

Preparation of (Pb0.88La0.12)TiO3 thin films for dynamic random access memory by low pressure-metalorganic chemical vapor deposition

La-modified lead titanate (PLT) thin films were prepared by hot-wall type low pressure-metalorganic chemical vapor deposition method. Pb(dpm)₂, La(dpm)₃, and titanium tetraisopropoxide were used as source materials. The films were deposited at 500°C under the low pressure of 1000 mTorr and then annealed at 650°C for 10 min in oxygen ambient. Sputter-deposited platinum electrodes and 180 nm thick PLT thin films were employed to form MIM capacitors with the best combination of high charge storage density (26.7 μC/cm² at 3V) and low leakage current density (1.5 × 10^-7 A/cm² at 3V). The measured dielectric constant and dielectric loss were 1000∼1200 and 0.06∼0.07 at zero bias and 100 kHz, respectively.     

Ionizing radiation effects on electrical and reliability characteristics of sputtered Ta2O5/Si interface

This paper describes the effect of ionizing radiation on the interface properties of Al/Ta₂O₅/Si metal oxide semiconductor (MOS) capacitors using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The devices were irradiated with X-rays at different doses ranging from 100?rad to 1?Mrad. The leakage behavior, which is an important parameter for memory applications of Al/Ta₂O₅/Si MOS capacitors, along with interface properties such as effective oxide charges and interface trap density with and without irradiation has been investigated. Lower accumulation capacitance and shift in flat band voltage toward negative value were observed in annealed devices after exposure to radiation. The increase in interfacial oxide layer thickness after irradiation was confirmed by Rutherford Back Scattering measurement. The effect of post-deposition annealing on the electrical behavior of Ta₂O₅ MOS capacitors was also investigated. Improved electrical and interface properties were obtained for samples deposited in N₂ ambient. The density of interface trap states (D_it) at Ta₂O₅/Si interface sputtered in pure argon ambient was higher compared to samples reactively sputtered in nitrogen-containing plasma. Our results show that reactive sputtering in nitrogen-containing plasma is a promising approach to improve the radiation hardness of Ta₂O₅/Si MOS devices.     

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

A novel linear switched termination active cross‐coupled low‐voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross‐coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared preamplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak‐to‐peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.     

Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs

In this paper, a transparent test technique for testing permanent faults developed during field operation of DRAMs has been proposed. A three pronged approach has been taken in this work. First, a word oriented transparent March test generation algorithm has been proposed that avoids signature based prediction phase; next the proposed transparent March test is structured in a way that facilitates its implementation during refresh cycles of the DRAM; finally the on-chip refresh circuit is modified to allow its re-use during implementation of the proposed transparent March test on DRAM. Re-use of refresh cycles for test purpose ensures periodic testing of DRAM without interruption. Thus, faults are not allowed to accumulate. Moreover, wait for idle cycles of the processor to perform the test are avoided and test finishes within a definite time. Re-using the refresh circuit for test purpose overcomes requirement of additional Design-For-Testability hardware and brings down the area overhead.Both analytic predictions and simulation results for the method proposed here indicate real estate benefits and test time savings in comparison to other reported techniques. The proposed refresh re-use based transparent test technique provides a cost effective solution by providing facility for periodic tests of DRAM without requiring additional test hardware.     

氧气氛低温退火Pt/Ba0.8Sr0.2TiO3Pt引起的低频介电弛豫效应

研究了在不同温度区间氧气氛和氮气氛退火后处理对PtBa0.8Sr0.2TiO3Pt介电特性的影响.经过高温550℃氮气退火处理后,再放入350℃的氧气中退火,发现样品的介电特性出现了非常明显的低频弛豫现象,并且这种低频弛豫现象在350℃的氮气中退火后将会消失.通过在出现低频弛豫现象的样品的上下电极加一偏压,可以发现低频弛豫现象更加明显,并且在撤消偏压后这种增强将会逐渐减弱,直至最终恢复到偏压前的弛豫状态 关键词： 脉冲激光沉积 介电弛豫 动态随机存储器