一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

Adsp-21060的主机接口在实时图像处理中的应用

简要介绍了数字信号处理器Adsp 2 10 6 0和大规模可编程逻辑器件EP1K5 0。详细讨论了Adsp 2 10 6 0的主机接口工作模式以及一个实时图像跟踪处理器的硬件组成原理 ,在这个系统中EP1K5 0充当了主机。调试结果表明 ,所提出的硬件结构设计思想工作效率高 ,完全能够胜任实时图像处理的实际需要。     

2.4GHz动态CMOS分频器的设计

对现阶段的主流高速CMOS分频器进行分析和比较,在此基础上设计一种采用TSPC(truesingle phase clock)和E-TSPC(extended TSPC)技术的前置双模分频器电路.该分频器大大提高了工作频率,采用0.6μm CMOS工艺参数进行仿真的结果表明,在5V电源电压下,最高频率达到3GHz,功耗仅为8mW.     

逻辑分析仪在教学实验中的应用

硬件教学实验必须由验证性向设计性转变，才能达到培养学生设计能力和处理问题的能力。而逻辑分析仪是数字系统设计的常用工具．对于实验和教学都起着不可忽视的作用。     

理想九点五态控制器原理的叙述

用计算的方式叙述理想九点五态控制器的控制原理。为便于人们理解二阶对象的运动中控制的变化过程,将抽象的对象转换为人们熟知的L-R-C电路,通过调节输入电压(即控制作用)的大小和方向来实现对对象性能的调节,并使系统达到理想的性能指标。最后用仿真来验证计算结果的正确性。     

Synchronous Full-Scan for Asynchronous Handshake Circuits

Handshake circuits form a special class of asynchronous circuits that has enabled the industrial exploitation of the asynchronous potential such as low power, low electromagnetic emission, and increased cryptographic security. In this paper we present a test solution for handshake circuits that brings synchronous test-quality to asynchronous circuits. We add a synchronous mode of operation to handshake circuits that allows full controllability and observability during test. This technique is demonstrated on some industrial examples and gives over 99% stuck-at fault coverage, using test-pattern generators developed for synchronous circuits. The paper describes how such a full-scan mode can be achieved, including an approach to minimize the number of dummy latches in case latches are used in the data path of the handshake circuit.     

Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic

Currently there are design barriers inhibiting the implementation of high-precision digital signal processing (DSP) objects with field programmable logic (FPL) devices. This paper explores overcoming these barriers by fusing together the popular distributed arithmetic (DA) method with the residue number system (RNS) for use in FPL-centric designs. The new design paradigm is studied in the context of a high-performance filter bank and a discrete wavelet transform (DWT). The proposed design paradigm is facilitated by a new RNS accumulator structure based on a carry save adder (CSA). The reported methodology also introduces a polyphase filter structure that results in a reduced look-up table (LUT) budget. The 2C-DA and RNS-DA are compared, in the context of a FPL implementation strategy, using a discrete wavelet transform (DWT) filter bank as a common design theme. The results show that the RNS-DA, compared to a traditional 2C-DA design, enjoys a performance advantage that increases with precision (wordlength).