2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S₂₁), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S₁₁ and S₂₂ are less than −10 dB. The input compression point (P_1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm².     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

RF磁控溅射制备钛酸锶钡BST纳米薄膜

钛酸锶钡(BST)薄膜作为一种高K介质材料在微电子和微机电系统等领域具有广阔的应用前景,人们已对BST薄膜的制备工艺技术和介电性能进行了大量的研究。BST纳米薄膜的制备工艺直接影响和决定着薄膜的介电性能(介电常数、漏电流密度、介电强度等)。对RF磁控反应溅射制备BST纳米薄膜的工艺技术进行了综述。从溅射靶的制备、溅射工艺参数的优化、热处理、薄膜组分的控制,及制备工艺对介电性能的影响等方面,对现有研究成果进行了较全面的总结。     

CMOS光接收机主放大器设计

利用CMOS工艺设计一种用于SDH STM 4速率级(622 Mb/s)光纤用户网的光接收机放大电路。此电路由输入/输出缓冲、主放大单元、偏置补偿电路4部分组成。通过直接耦合技术提高增益,降低功耗;利用有源电感负载提高系统带宽。采用商用SmartSpice电路仿真软件和CSMC HJ 0.6μm工艺参数对该电路进行仿真。结果表明,该电路在5 V工作电压下中频增益为81 dB,3 dB带宽为470 MHz。     

采用RF2607的WLAN自动增益控制设计

介绍了宽动态变化范围的新型可变增益放大器RF2607的特性、功能,给出了利用RF2607设计无线局域网(WLAN)通信中自动增益控制部分的实用电路.     

5Gb/s 0.25μm CMOS限幅放大器

采用TSMC 0.25μm CMOS技术设计实现了高速低功耗光纤通信用限幅放大器.该放大器采用有源电感负载技术和放大器直接耦合技术以提高增益,拓展带宽,降低功耗并保持了良好的噪声性能.电路采用3.3V单电源供电,电路增益可达50dB,输入动态范围小于5mVpp,最高工作速率可达7Gb/s,均方根抖动小于0.03UI.此外核心电路功耗小于40mW,芯片面积仅为0.70mm×0.70mm.可满足2.5,3.125和5Gb/s三个速率级的光纤通信系统的要求.     

宽工作电压范围单电源CMOS误差放大器

采用0.8μm标准数字CMOS工艺(VTN0=0.836V,VTP0=0.930V),设计并流片验证了具有宽工作电压范围(3～6V),可作SOC系统动态电源管理芯片内部误差放大器应用的单电源CMOS运算放大器。该误差放大器芯核同时具有适合低电压工作,并对工艺参数变化不敏感的优点。对于相同的负载情况,在3V的工作电压下,开环电压增益AD=83.1dB,单位增益带宽GB=2.4MHz,相位裕量Φ=85.2°,电源抑制比PSRR=154.0dB,转换速率Sr=2.2V/μs;在6V工作电压下,AD=85.1dB,GB=2.4MHz,Φ=85.4°,PSRR=145.3dB,Sr=3.4V/μs。     

21~28GHz波段平衡式放大器

采用OMM IC的0.2μm PHEM T工艺设计了工作在21~28 GH z的平衡式放大器。正交耦合电桥采用兰格电桥。兰格电桥和平衡式放大器的在片测试结果和仿真结果基本吻合,平衡式放大器在21~28 GH z的增益为18~20 dB,输入和输出回波损耗小于-20 dB,在26 GH z处的输出1 dB压缩点功率为21 dBm。     

1.8 V千兆以太网接收器模拟前端预均衡电路

介绍了一种用于1.8 V电源电压下的千兆以太网接收器的模拟前端预均衡电路。电路分为三个部分:预处理电路、基带漂移补偿电路和可变增益放大电路,主要实现回波消除、基带漂移补偿和电路增益自动控制等功能。为了与百兆模式兼容,提出了一种预处理电路。仿真结果表明,该电路可以很好地实现回波消除的功能,能够对由于基带漂移引起的信号失真给以补偿,可以提供16级不同的增益,并进行频率补偿。电路采用0.18μm标准CMOS工艺实现。     

射频电缆组件组装工艺浅谈

近年来国内外射频电缆组件的发展很快,射频电缆组件的性能不断提高,对射频电缆组件组装工艺也提出了更高的要求.射频电缆组件组装过程多是手工操作,产品的一致性及性能很难控制,要求有良好的工艺保证,为此介绍了射频电缆组件组装工艺,包括电缆的裁剪及剥皮、内导体的连接、外导体的连接和电气性能的测试;探讨了在组装过程中应注意的问题,以及针对内导体焊接易出现虚焊问题进行研究.