Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Small‐Sized High‐Power PIN Diode Switch with Defected Ground Structure for Wireless Broadband Internet

This letter presents a small‐sized, high‐power single‐pole double‐throw (SPDT) switch with defected ground structure (DGS) for wireless broadband Internet application. To reduce the circuit size by using a slow‐wave characteristic, the DGS is used for the quarter‐wave (°/4) transmission line of the switch. To secure a high degree of isolation, the switch with DGS is composed of shunt‐connected PIN diodes. It shows an insertion loss of 0.8 dB, an isolation of 50 dB or more, and power capability of at least 50 W at 2.3 GHz. The switch shows very similar performance to the conventional shunt‐type switch, but the circuit size is reduced by about 50% simply with the use of DGS patterns.     

宽带DDS跳频源设计

直接数字合成（DDS）简单可靠、控制方便，具有很高的频率分辨率，高速转换，非常适合快速跳频的要求。在对DDS基本原理进行了简要介绍和分析后，提出宽带跳频源设计方案。     

一个基于PE分层技术的电子政务网络平台

电子政务网络建设的主要目标就是建立一个开放的、基于标准的统一网络平台，并在该平台上实现政府不同部门之间的信息交换和资源共享，同时保证各部门信息的独立和安全。通过介绍电子政务网络建设中的主流技术——MPLSVPN，提出了一种基于该技术原理的PE分层技术，详细讨论了基于该分层技术的电子政务网络平台的实现过程和主要技术，并对其性能参数进行了测试与分析。     

共面波导(CPW)馈电单极子天线的设计与研究

给出一种工作于900MHz的共面波导(CPW)馈电单极子天线的设计。该单极子天线以共面波导的中心导带为辐射单极子，以中心导带两边的金属导体作反射板，结构简单紧凑。但是由于天线与共面波导之间缺少有效的隔离，造成天线性能受共面波导尺寸的影响较严重。本文通过模拟计算和实验测量详细分析了共面波导尺寸的变化对天线性能的影响，给出了结合共面波导尺寸设计的工作在900MHz的单极子天线结构数据。     

医用激光治疗机的触摸屏控制系统设计

介绍了医用红宝石激光器触摸屏控制系统的基本结构，分析了医用红宝石激光器中主要电磁干扰（EMI）的产生机制，提出了具体的电磁兼容（EMC）技术措施并得到实验验证。     

城域波分网络中的光环路保护分析

介绍了在城域波分网络中应用的四种环形保护倒换方案及其实现方式，并对各种保护倒换方案的特性进行了分析比较。     

共面波导有限金属厚度效应的研究

用保角变换法对共面波导金属厚度效应进行了理论分析，编制了相应的计算机程序，给出了数值解，并对此进行了多元曲线拟合，导出了考虑金属厚度后的形状比k、有效介电常数、特征阻抗、损耗的闭定表达式。用此修正表达式求得特征阻抗及损耗的数值解，并与K．C．格普塔的修正值及实验测量值进行了详细比较，结果表明此修正公式与实验值相符较好。     

非线性干涉滤光片开关特性及逻辑功能

应用干涉滤光片作为一种光学双稳器件,演示了光学逻辑开关功能。     

利用新型场效应管(QFET)的正向变换器

介绍了单端正向变换器基本电路，重点叙述带三路调节DC电压的100KHZ180W离线电源。它采用具有低导电阻RDS和低栅极电荷Qg的新型场效应管（QFET）作为变换电路的主开关器件，降低了电源开关损耗并提高了效率3%-5%。