内置旁路型软起动器的替代性

本文根据软起动器的发展趋势，就目前市场上应用的三种类型的软起动器进行分析，说明各自的优缺点，同时给出结论，内置旁路型淘汰其它类型的软起动器的必要性。     

Exact probabilistic testability measures for multi-output circuits

The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the X-gate, and applying to the resulting graph the analysis based on supergates.     

有强内电场的GaN-基阶梯量子阱中的线性与非线性光吸收

采用密度矩阵方法,考察了带强内建电场GaN-基阶梯量子阱中的线性与非线性光吸收系数.基于能量依赖的有效质量方法,在考虑了带的非抛物性情况下,推导了结构中的精确解析的电子本征态,给出了系统中简单解析的线性与非线性光吸收系数表达式.以AlN/GaN/AlxGa1-xN/AlN阶梯量子阱为例进行了数值计算.结果发现阶梯量子阱的阱宽Lw、阶梯垒宽Lb、阶梯垒的掺杂浓度x的减小将提高体系的吸收系数.而且,随着Lw,Lb和x减小,吸收光子的能量有明显的蓝移,总吸收系数的半宽度及饱和吸收强度均减小.计算获得的部分结果与最近的实验观察完全一致.     

AlGaN/GaN抛物量子点的尺寸相关三阶非线性极化率研究

在有效质量近似框架下,通过求解AlxGa1－xN/GaN自组织圆柱形量子点的薛定谔方程,计算了量子点中导带电子在两个正交方向：Z‖和Z⊥方向上产生的三阶非线性极化率.计算中,电子的运动受到自组织量子点的抛物型束缚势和内建压电场的影响.计算表明,量子点的三阶非线性极化率的数量级达到了10－14m2/V2.进一步在Z‖和Z⊥方向上,考察了三阶非线性极化率与两个方向上的抛物束缚势的频率ωp、ωz,量子点的高度L,半径R,Al的含量x之间的关系.     

Multiple-output parity bit signature for exhaustive testing

In this article we propose a multiple-output parity bit signature generation method for exhaustive testing of VLSI circuits. Given a multiple-output combinational circuit, a parity bit signature is generated by first EXORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. The method preserves all the desirable properties of the conventional single-output circuits response analyzers and can be readily implemented using the current VLSI technology.     

A Novel BIRA Method with High Repair Efficiency and Small Hardware Overhead

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.     

Proportional BIC sensor for current testing

A new design of a BIC sensor for current testing static CMOS circuits is proposed. It is based on a lateral BJT device which is easy to incorporate in any standard CMOS process. The design diverts a fraction of the I _DDQ current from the cell under test and a resistive component generates a voltage proportional to I _DDQ . Additional features are the possibility of continuous measure of i _dd and increased speed of this sensor compared with sensors based on the current integration principle. The design does not have substrate currents due to the parasitic vertical BJTs. Experimental work on the sensor is reported.     

Cyclic code weight spectra and BIST aliasing

In built-in self-test for logic circuits, test data reduction can be achieved using a linear feedback shift register. The probability that this data reduction will allow a faulty circuit to be declared good is the probability of aliasing. Based on the independent bit-error model, we show that the code spectra for the cyclic code generated by the feedback polynomial can be used to obtain an exact expression for the aliasing probability of a multiple input signature register when the test length is a multiple of the cycle length. Several cases are examined and, as expected, primitive feedback polynomials provide the best performance. Some suggestions to avoid peaks in the aliasing probability are given.     

Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge–Response pair acquisition using Built-In Self-Test before shipping

We implemented pseudo-linear feedback shift-register-based physical unclonable functions (PL-PUFs) on silicon and analyzed their performances in terms of reproducibility, uniqueness, and resistance to machine-learning attacks. A PL-PUF is compact and high-throughput PUF, slightly oversensitive to voltage fluctuations. To overcome this drawback, we developed a capturing signal generation circuit that was tolerant to the reproducibility degradation caused by supply voltage changes. We also implemented a Built-In Self-Test (BIST) circuit with an irreversible destruction mechanism to enable exceedingly fast challenge–response pairs (CPRs) for the PUFs before shipping. After the CPRs were evaluated, the BIST circuit became invulnerable to exploitation by attackers.