ON SOME INTEGRATION BY PARTS FORMULATE FOR THE ASP-INTEGRAL

The main results of this paper are as follows；Let F be approximately continuous on[a,b]and g be of bounded variation on[a,b]. Then (APS)∫^ba Fexists if and only if (APS)∫^ba gdf existe. Furthermore,suppose (APS)∫^ba Fdy or (APS)∫^ba gdF exists, then we have (APS)∫^ba Fdg (APS)∫^bagdf=F(b)g(b)-F(a)g(a)     

软件功能测试管理模型在上海轨道交通AFC系统中的应用

上海轨道交通的线路数逐年递增,随之自动售检票系统的规模越来越大,如何管理由于自动售检票系统的应用软件版本不断升级带来的软件功能测试的管理问题亟待解决本文借鉴ITIL思想,提出一个针对软件功能测试的管理模型应用表明,该模型在上海轨道交通自动售检票系统的测试管理中是成功和有效的     

Automated optimization of split ratio in capillary gas chromatography

An electronic gas-flow controller system called Advanced Flow Control (AFC), which controls not only carrier gas pressure at the column inlet but also the total gas flow including the split flow, was designed and evaluated. BASIC programming of repetitive analyses of standard mixtures under varied split ratios and pressure programs allowed automated optimization of those conditions for the desired column loading and resolution between adjacent peaks.     

基于二维码技术的AFC系统研究与探讨

由于城市交通压力越来越大,城市轨道交通得到了迅速发展,同时越来越多的人选择乘坐地铁出行。传统的AFC系统主要以现金支付为主,排队买票浪费大量时间,乘客出行体验差,且需要大量现金,因此提出的二维码支付方式。二维码支付设计方案是在保持原有售检票机功能的基础上,增加使用移动设备二维码检票过闸功能。另外,详细说明了二维码支付的业务流程。二维码支付再地铁中的使用为地铁购票提供了便利,同时提高了地铁购票的效率和服务质量。     

南京地铁宁天线AFC参数下发失败处理方法研究

本文从实际工作出发,介绍南京地铁自动售检票AFC系统中AFC参数的定义与类别;分析AFC系统构架以及AFC参数的下发流程;解析参数下发过程中可能遇到各类问题及处理方法.     

一种平衡设计压控振荡器和自动频率校准的快速锁定宽带频率综合器

A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS process.It employs a wideband LC voltage-controlled oscillator(VCO) with optimized VCO gain(KVCO/and a sub-band step to improve automatic frequency calibration(AFC) efficiency at negligible expense of phase noise performance.An agile AFC is realized by direct mapping based on the division ratio,and optional redundant counting and comparing calibration is introduced accommodating PVT variations,which samples the reference clock using the prescaled VCO output as a discriminating clock.A charge pump with switched charging current is adopted to compensate for the loop bandwidth variation.Measurement results show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 s for redundant calibration.The frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz,with phase noise of-86 dBc/Hz at 10 kHz offset and-122 dBc/Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.     

Adaptive digital calibration techniques for narrow band low-IF receivers with on-chip PLL

Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented. The calibration and control system, which is adopted to ensure an achievable signal-to-noise ratio and bit error rate, consists of a digitally controlled, high resolution dB-linear automatic gain control (AGC), an inphase (I) and quadrature (Q) gain and phase mismatch calibration, and an automatic frequency calibration (AFC) of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer. The calibration system has a low design complexity with little power and small die area. Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB, respectively, which means the image rejection ratio is better than 60 dB. In addition, the calibration time of the AFC is 1.12μs only with a reference clock of 100 MHz.     

一种脉冲调制信号鉴频器的设计

介绍了脉冲调制信号鉴频器构成的原理，详细分析了影响其温度稳定性的各种因素，并给出了相应的解决措施。采用具有温度补偿措施的双二极管整流电路，解决了对鉴频器温度性能影响最大的整流电路温度变化问题。所设计的脉冲调制鉴频器在-20～70℃温度范围内鉴频输出电压变化小于5％。最后，简要介绍了鉴频器对不同重复频率的调制信号(占空比相同)的兼容性问题及其设计。     

数字分频式行场扫描电路

本文介绍了彩电专用集成电路中一种新型的数字分频式行场扫描电路,包括它的组成、工作原理及其主要特点。     

Fractional-N phase-locked loop for split and direct automatic frequency control in A-GPS

A low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is <5 parts per billion (ppb) or on the order of a Hertz. The cycle-to-cycle rms jitter is <6 ps and the typical settling time is <30 μs. A spur reduction technique is adopted and implemented as well, demonstrating spur reduction without employing dithering. The proposed PLL includes a low-leakage phase-frequency detector, a low-drop-out regulator, power-on-reset circuitry and precharge circuitry. The PLL is implemented in a 90-nm CMOS process technology with 1.2 V single supply. The overall PLL draws about 1.1 mA from the supply.