Analytical analysis of surface potential for grooved-gate MOSFET

The improvement of the characteristics of grooved-gate MOSFETs compared to the planar devices is attributed to the corner effect of the surface potential along the channel. In this paper we propose an analytical model of the surface potential distribution based on the solution of two-dimensional Poisson equation in cylindrical coordinates utilizing the cylinder approximation and the structure parameters such as the concave corner $\theta _0 $. The relationship between the minimum surface potential and the structure parameters is theoretically analysed. Results confirm that the bigger the concave corner, the more obvious the corner effect. The corner effect increases the threshold voltage of the grooved-gate MOSFETs, so the better is the short channel effect (SCE) immunity.     

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability (NBTI) has become one of the most serious reliability problems of metal- oxide-semiconductor field-effect transistors (MOSFETs). The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H+ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H+ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H+ generated during NBTI stress.     

HOT-CARRIER GENERATION MECHANISM AND HOT-CARRIER EFFECT IMMUNITY IN DEEP-SUB-MICRON GROOVED-GATE PMOSFETS

Based on the hydrodynamic energy transport model, immunity from the hot-carrier effect in deep-sub-micron grooved-gate p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) is analysed. The results show that hot carriers generated in grooved-gate PMOSFETs are much smaller than those in planar ones, especially for the case of channel lengths lying in the deep-sub-micron and super deep-sub-micron regions. Then, the hot-carrier generation mechanism and the reason why grooved-gate MOS devices can suppress the hot-carrier effect are studied from the viewpoint of physical mechanisms occurring in devices. It is found that the highest hot-carrier generating rate is at a medium gate bias voltage in three stress areas, similar to conventional planar devices. In deep-sub-micron grooved-gate PMOSFETs, the hot-carrier injection gate current is still composed mainly of the hot-electron injection current, and the hole injection current becomes dominant only at an extremely high gate voltage. In order to investigate other influences of the hot-carrier effect on the device characteristics, the degradation of the device performance is studied for both grooved-gate and planar devices at different interface states. The results show that the drift of the device electrical performance induced by the interface states in grooved-gate PMOSFETs is far larger than that in planar devices.     

Influence of structural parameters on the immunity of short-channel effects in grooved-gate nMOSFET

This paper presents the influences of structural parameters on the immunity of short-channel effects in grooved-gate n-channel metal－oxide－semiconductor field effect transistor (nMOSFET) using the simulator PISCES-II. The zero or negative groove-junction depth is beneficial to the improvement of the threshold characters, but there exists a limited range. The doping concentration of both substrate and channel has a significant influence on the threshold characters as well as on the device transconductance. Thus, the variation in these adjustable parameters may help to optimize the device design.     

Degradation characteristics and mechanism of PMOSFETs under NBT--PBT--NBT stress

Degradation characteristics of PMOSFETs under negative bias temperature--positive bias temperature--negative bias temperature (NBT--PBT--NBT) stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.     

新型槽栅nMOSFET凹槽拐角效应的模拟研究

应用二维器件仿真程序PISCES Ⅱ，模拟计算了新型槽栅结构器件中凹槽拐角效应的影响与作用，讨论了槽栅结构MOSFET的沟道电场特征及其对热载流子效应、阈值电压特性等的影响.槽栅结构的凹槽拐角效应对抑制短沟道效应和抗热载流子效应是十分有利的，并且拐角结构在45°左右时拐角效应最大.调节拐角与其他结构参数，器件的热载流子效应、阈值电压特性、亚阈值特性、输出特性等都会有较大的变化. 关键词： 槽栅MOSFET 拐角效应 阈值电压 热载流子退化     

新型槽栅PMOSFET热载流子退化机理与抗热载流子效应研究

分析了槽栅器件中的热载流子形成机理,发现在三个应力区中,中栅压附近热载流子产生概率达到最大.利用先进的半导体器件二维器件仿真器研究了槽栅和平面PMOSFET的热载流子特 性,结果表明槽栅器件中热载流子的产生远少于平面器件,且对于栅长在深亚微米和超深亚 微米情况下尤为突出.为进一步探讨热载流子加固后对器件特性的其他影响,分别对不同种 类和浓度的界面态引起的器件栅极和漏极特性的漂移进行了研究,结果表明同样种类和密度 的界面态在槽栅器件中引起的器件特性的漂移远大于平面器件.为开展深亚微米和亚0.1微米 新型槽栅 关键词： 槽栅PMOSFET 热载流子退化机理 热载流子效应     

Actions of negative bias temperature instability (NBTI) and hot carriers in ultra-deep submicron p-channel metal——oxide——semiconductor field-effect transistors (PMOSFETs)

Hot carrier injection (HCI) at high temperatures and different values of gate bias V_g has been performed in order to study the actions of negative bias temperature instability (NBTI) and hot carriers. Hot-carrier-stress-induced damage at V_g=V_d, where V_d is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different: the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal--oxide--semiconductor field-effect transistors (PMOSFETs). We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.