Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

Sensitivity of heavy-ion-induced single event burnout in SiC MOSFET

The energy deposition and electrothermal behavior of SiC metal-oxide-semiconductor field-effect transistor(MOSFET)under heavy ion radiation are investigated based on Monte Carlo method and TCAD numerical simulation.The Monte Carlo simulation results show that the density of heavy ion-induced energy deposition is the largest in the center of the heavy ion track.The time for energy deposition in SiC is on the order of picoseconds.The TCAD is used to simulate the single event burnout(SEB)sensitivity of SiC MOSFET at four representative incident positions and four incident depths.When heavy ions strike vertically from SiC MOSFET source electrode,the SiC MOSFET has the shortest SEB time and the lowest SEB voltage with respect to direct strike from the epitaxial layer,strike from the channel,and strike from the body diode region.High current and strong electric field simultaneously appear in the local area of SiC MOSFET,resulting in excessive power dissipation,further leading to excessive high lattice temperature.The gate-source junction area and the substrate-epitaxial layer junction area are both the regions where the SiC lattice temperature first reaches the SEB critical temperature.In the SEB simulation of SiC MOSFET at different incident depths,when the incident depth does not exceed the device's epitaxial layer,the heavy-ion-induced charge deposition is not enough to make lattice temperature reach the SEB critical temperature.     

The role of a radial ion-track distribution in semiconductors studied by numerical simulations

The effect of radial ion-track distribution on the transient current in semiconductors caused by a high-energy heavy ion strike was studied. Reasonable agreement was observed in experimental and calculated transient currents for ion energies ranging from several to several hundred MeV when the radius of the ion track used in the numerical simulations was shorter or equivalent to that of the penumbra radius.     

Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Three-dimensional (3D) TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor (NMOS) transistor or P-channel metal-oxide semiconductor (PMOS) transistor can mitigate the cross section of single event upset (SEU) in 14-nm complementary metal-oxide semiconductor (CMOS) bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Unlike dual-interlock cell (DICE) design, this approach is more effective under heavy ion irradiation of higher LET, in the presence of enough taps to ensure the rapid recovery of well potential. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.     

Material requirements and design considerations for Si/SiGe heterojunction CMOS

Five vertical architecture options for SiGe/Si heterojunction CMOS devices are compared using technology computer-aided design. The benefit of using SiGe over conventional MOSFETs is set to increase for future technology generations. We investigate the impact of material degradation, to determine the minimum requirements needed for HMOS to offer real advantages over conventional CMOS.     

Experimental extraction of stern-layer capacitance in biosensor detection using silicon nanowire field-effect transistors

Accurate diagnose of a disease in the early stage is critical to treat the disease properly. To this end, a multitude of biosensors with advanced technologies have been developed to detect the number of biomolecules precisely. In this work, we propose a method for extracting the Stern layer capacitance (C_stern) using the experimental data of silicon nanowire ion-sensitive field-effect transistors (ISFETs) to help improve the accurate detection of target molecules. The proposed method was applied to both pH and virus sensing scheme, and the C_stern value of pH and a virus were extracted as 32 and 26 μF/cm², respectively. These findings indicated that the extracted C_stern was affected by the size of the ion and protein, which also was verified by a computer-aided simulation. These insights would be useful in the development of charge-based ISFET biosensors.     

Calculation of optical properties of a quantum dot embedded in a GaN/AlGaN nanocolumn

The TiberCAD simulation tool for calculation of optical and electronic properties of nanostructured devices has been used to study spontaneous emission of a GaN quantum dot embedded in an AlGaN nanocolumn. Macroscopic calculations provide corrections to the quantum calculation, showing the role of strain and the polarization field in spectra and the electron and hole states arrangement.     

Device design of single-gated feedback field-effect transistors to achieve latch-up behaviors with high current gains

In this study, a device design of single-gated feedback field-effect transistors (FBFETs) is proposed to achieve latch-up behaviors with high current gains. The latch-up mechanism is examined by conducting an equivalent circuit analysis, and the band diagram, I–V characteristics, memory window, subthreshold swing, and on/off current ratio are investigated using a commercial device simulator. The proposed FBFETs exhibit memory windows wider than 3.0 V, subthreshold swings less than 0.1 mV/decade, the on/off current ratios of approximately 10¹⁰, and on-currents of approximately 10⁻⁵ A at room temperature. The superior device characteristics and controllable memory windows open the promising possibility of FBFETs as the next-generation electronic devices.     

单粒子瞬变中的双极放大效应研究

采用三维数值模拟的方法对比研究了单个NMOS晶体管和反相器链中的单粒子瞬变（single event transient,SET）电流脉冲,发现深亚微米工艺下双极放大电流在单管的SET电流脉冲中占主要成分,而在反相器链的SET模拟中不明显,分析二者的区别解释了源/体结偏压的形成过程和放大机理,并证明了双极放大效应受源/体结偏压影响的结论.在此基础上分析了NMOS管中源极的正向电流及其机理,发现台阶区的源极正向电流主要是由扩散作用形成的. 关键词： 单粒子瞬变 双极放大 混合模拟 台阶区电流