Low temperature transport properties of thin SOI MOSFETs

Fabrication and 4.2 K mobility measurements of silicon-on-insulator (SOI) metal–oxide-field-effect-transistors are reported. The three sets of samples fabricated in this work include devices for which the SOI film thicknesses (t_SOI) are in the ranges of 10–15, 16–19 and 56–61 nm. The peak mobility of the devices that have the SOI film thickness above 16.5 nm is 1.9 m²/V s. The set of devices with thinnest channel (t_SOI=10–15 nm) suggest that the peak mobility decreases with decreasing t_SOI.     

High-index contrast grating based broadband out-coupler on SOI

An efficient broadband out-coupler on silicon-on-insulator (SOI) with high-index contrast grating (HCG) is proposed. The presence of a silicon-air (high-index contrast) grating on the top silicon layer in SOI allows a strong interaction between the guided mode and the grating. The broadband design of the out-coupler is presented by optimising the various grating parameters. The design analysis and simulation of such an out-coupler is performed with finite difference method. Coupling efficiency of 54% is achieved over an ultra-wide wavelength range from 1500 nm to 1650 nm.     

基于PML边界的有限差分法及其在光波导泄漏损耗计算中的应用

利用结合完美匹配层(PML)边界的有限差分法计算了光波导的泄漏损耗.通过采用非均匀格点差分格式和反正切坐标变换的方法,有效地减小了计算量并提高了计算精度.分析了PI(polyimide)掩埋型波导和SOI(silicon-on-insulator)脊型波导两种典型结构的泄漏损耗,给出了波导结构尺寸对泄漏损耗的影响,并对有效减小泄漏损耗的方法进行了讨论.     

Ultrafast all-optical XOR logic gate based on a symmetrical Mach-Zehnder interferometer employing SOI waveguides

We present an integrated Silicon-on-Insulator (SOI) based Mach-Zehnder interferometer (MZI) in order to perform ultrafast all-optical XOR logic gate operation with a bit rate of ∼ 0.33 Tb/s. A numerical simulation is carried out in order to study various parameters such as extinction ratio and eye-opening parameters, characterizing the performance of the XOR logic gate. The output XOR logic gate signal can have improved extinction and eye margin if the initial powers of primary signals and the probe continuous-wave (CW), and SOI waveguide length are judiciously adjusted.     

A photonic wire-based directional coupler based on SOI

A photonic wire-based directional coupler based on SOI was fabricated by e-beam lithography (EBL) and the inductively coupled plasma (ICP) etching method. The size of the sub-micron waveguide is 0.34 μm × 0.34 μm, and the length in the coupling region and the separation between the two parallel waveguides are 410 and 0.8 μm, respectively. The measurement results are in good agreement with the results simulated by 3D finite-difference time-domain method. The transmission power from two output ports changed reciprocally with about 23 nm wavelength spacing between the coupled and direct ports. The extinction ratio of the device was between 5 and 10 dB, and the insertion loss of the device in the wavelength range 1520-1610 nm was between 22 and 24 dB, which included an about 18.4 ± 0.4 dB coupling loss between the taper fibers and the polished sides of the device.     

Design, analysis and optimization of silicon-on-insulator photonic crystal dual band wavelength demultiplexer

A highly efficient photonic crystal dual band wavelength demultiplexer (DBWD) using silicon-on-insulator (SOI) substrates is proposed for demultiplexing two optical communication wavelengths, 1.31 μm and 1.55 μm. Demultiplexing of two wavelength channels is obtained by modifying the propagation properties of guided modes in two arms of Y type photonic crystal structure. Propagation characteristics of proposed DBWD are analyzed utilizing 3D finite difference time domain (FDTD) method. Enhancement in spectral response is further obtained by optimizing the Y junction of demultiplexer giving rise to high transmission and extinction ratio for the wavelengths, 1.31 μm and 1.55 μm. Hence it validates the efficiency of proposed optimized DBWD design for separating two optical communication wavelengths, 1.31 μm and 1.55 μm. Tolerance analysis was also performed to check the effect of variation of air hole radius, etch depth and refractive index on the transmission characteristics of the proposed design of SOI based photonic crystal DBWD.     

Si基双环级联光学谐振腔应变检测研究

绝缘衬底上的硅材料制备的光学微环谐振腔结构具有高灵敏度、结构尺寸小和极低模式体积等特性,被广泛应用到光信息传递、惯性导航领域,但极少被应用到力学信号的测试,为此,研究了一种基于硅基光学微环谐振腔结构的悬臂梁式应力/应变敏感计,利用微环谐振腔环形波导径向形变量作为感应应力的中间物理量,在外界应力作用下,环形波导的半径将发生改变,使结构的光学谐振参数产生变化,从而使光学微环谐振腔谐振谱线发生明显红移,体现出良好的应力/应变敏感特性;通过设计双环级联光学微腔,并采用MEMS光刻、ICP腐蚀工艺制备了嵌入式光学微腔应变计结构,结合理论计算了悬臂梁结构的应力应变敏感特性,经仿真及实验得到,应变计结构的应力/应变灵敏度分别为0.185 pm·kPa-1,18.04 pm·microstrain-1,与单环微腔结构相比,线性量程增加了近50.3%,应力灵敏度提高了近10.6%,初步验证了嵌入式光学微腔结构进行高灵敏度应力/应变检测的可行性,有望实现新型光学力敏传感器件的微型化、集成化。     

一种改进的2×2 SOI Mach-Zehnder热光开关

本文设计并制作了基于强限制多模干涉耦合器的2×2 SOI马赫-曾德热光开关.这种光开关采用了深刻蚀结构的多模干涉耦合器和输入/输出波导,较大地提高了干涉耦合器的性能并减少了连接耦合损耗.同时,在调制臂区域采用浅刻蚀结构,保持其单模调制状态.深刻蚀多模干涉耦合器具有优越的特性,在实验中测得不均衡度只有0.03 dB,插入损耗－0.6 dB.基于这种耦合器的新型热光开关,其插入损耗为－6.8 dB,其中包括光纤-波导耦合损耗－4.3 dB,开关时间为6.8 μs.     

Fracture mechanics analysis on Smart-Cut~ technology.Part 1:Effects of stiffening wafer and defect interaction

In the present paper,continuum fracture mecha-nics is used to analyze the Smart-Cut process,a recentlyestablished ion cut technology which enables highly efficientfabrication of various silicon-on-insulator(SOI)wafers ofhigh uniformity in thickness.Using integral transform andCauchy singular integral equation methods,the mode-I andmode-Ⅱ stress intensity factors,energy release rate,and crackopening displacements are derived in order to examine seve-ral important fracture mechanisms involved in the Smart...     

A novel lateral diffused metal oxide semiconductor (LDMOS) by attracting the electric field Lines

In this paper, a novel silicon on insulator (SOI) lateral diffused metal oxide semiconductor (LDMOS) transistor with high voltage and high frequency performance is presented. In this work we try to reduce the electric field crowding in the drift region. The proposed structure consists of a metal in the buried oxide and also connected to the source. The inserted metal attracts the electric field lines in the buried oxide. It causes 67% improvement in the breakdown voltage in comparison with a conventional SOI-LDMOS (C-LDMOS). Our simulations with two dimensional ATLAS simulator show that the gate-drain capacitance improves in the proposed structure. The unilateral power gain also enhances. So, the proposed structure is suitable for high voltage and high frequency applications.