Structural properties and electrical characteristics of high-k Dy2O3 gate dielectrics

This paper describes the structural properties and electrical characteristics of thin Dy₂O₃ dielectrics deposited on silicon substrates by means of reactive sputtering. The structural and morphological features of these films after postdeposition annealing were studied by X-ray diffraction and X-ray photoelectron spectroscopy. It is found that Dy₂O₃ dielectrics annealed at 700 °C exhibit a thinner capacitance equivalent thickness and better electrical properties, including the interface trap density and the hysteresis in the capacitance-voltage curves. Under constant current stress, the Weibull slope of the charge-to-breakdown of the 700 °C-annealed films is about 1.6. These results are attributed to the formation of well-crystallized Dy₂O₃ structure and the reduction of the interfacial SiO₂ layer.     

Potassium Ion-Selective Field-Effect Transistor (ISFET) Sensors: Studies on Gate Dimensions and Ion-Implantation Levels

Abstract

Silicon nitride membrane ISFET sensor chips have been produced with varying gate dimensions. A series of width/length (W/L) aspect ratios have been examined, combined with three levels of boron ion-implant. The level of ion-implantation affects the threshold voltage; this is important as a low threshold voltage allows the use of low noise operating conditions. Gate dimensions are also important factors for they determine the level of drain current for a given gate and drain voltages. A novel design feature, aimed at achieving wide gates, is the use of folded gates as well as having a straight structure. The evaluation of devices with gates covered with poly(vinyl chloride) (PVC)-valinomycin-dioctyl adipate was based on their response to potassium chloride standards when it was shown that there may be a maximum width of gate above which there is no improvement of response. Also, the effect of folding the gate structure is discussed and shown to be tenable, thus permitting greater miniaturisation.     

Quantitative SIMS depth profiling of diffusion barrier gate-oxynitride structures in TFT-LCDs

Gate oxynitride structures of TFT-LCDs were investigated by SIMS, and successful solutions are demonstrated to overcome difficulties arising due to the charging effects of the multilayer systems, the matrix effect of the method, and the small pattern sizes of the samples. Because of the excellent reproducibility achieved by applying exponential relative sensitivity functions for quantitative analysis, minor differences in the barrier gate-oxynitride composition deposited on molybdenum capped aluminium-neodymium metallisation electrodes were determined between the centre and the edge of the TFT-LCD substrates. No differences were found for molybdenum-tungsten metallisations. Furthermore, at the edge of the glass substrates, aluminium, neodymium, and molybdenum SIMS depth profiles show an exponential trend. With TEM micrographs an inhomogeneous thickness of the molybdenum capping is revealed as the source of this effect, which influences the electrical behaviour of the device.The production process was improved after these results and the aging behaviour of TFT-LCDs was investigated in order to explain the change in control voltage occurring during the lifetime of the displays. SIMS and TEM show an enrichment of neodymium at the interface to the molybdenum layer, confirming good diffusion protection of the molybdenum barrier during accelerated aging. The reason for the shift of the control voltage was finally located by semi-quantitative depth profiling of the sodium diffusion originating from the glass substrate. Molybdenum-tungsten was a much better buffer for the highly-mobile charge carriers than aluminium-neodymium. Best results were achieved with PVD silicon oxynitride as diffusion barrier and gate insulator deposited on aluminium-neodymium metallisation layers.     

Growth behavior of high k LaAlO3 films on Si by metalorganic chemical vapor deposition for alternative gate dielectric application

LaAlO₃ (LAO) is explored in this work to replace SiO₂ as the gate dielectric material in metal–oxide–semiconductor field effect transistor. Amorphous LAO gate dielectric films were deposited on Si (0 0 1) substrates by low pressure metalorganic chemical vapor deposition using La(dpm)₃ and Al(acac)₃ sources. The effect of processing parameters such as deposition temperature and precursor vapor flux on growth, structure, morphology, and composition of LAO films has been investigated by various analytical methods deeply. The film growth mechanism on Si is reaction limiting instead of mass transport control. The reaction is thermally activated with activation energy of 37 kJ/mol. In the initial growth stage, Al element is deficient due to higher nucleation barrier on Si. The LAO films show a smooth surface and good thermal stability and remain amorphous up to a high temperature of 850 °C. The electrical properties of amorphous LAO ultrathin films on Si have also been evaluated, indicating LAO is suitable for high k gate dielectric applications.     

Aminocalix[4]arene: the effect of pH on the dynamics of gate and portals on the hydrophobic cavity

The pH of a solution shows a significant effect on the dynamics of the gate (formed by eight benzylic functions) and portal on the hydrophobic cavity of receptor. At pH 5.8 the gate closes and prohibits the entry of anionic guests. However, at pH 7.3 the gate opens and allows the entry of anionic guests into the hydrophobic cavity. It is the first time that anionic receptor efficiently recognizes anionic guests.     

A heuristic approach for airport gate assignments for stochastic flight delays

To make good flight to gate assignments, not only do all the relevant constraints have to be considered, but stochastic flight delays that occur in actual operations also have to be taken into account. In past research, airport gate assignments and stochastic disturbances have often been handled in the planning and the real-time stages separately, meaning that the interrelationship between these stages, as affected by such delays, has been neglected. In this research, we develop a heuristic approach embedded in a framework designed to help the airport authorities make airport gate assignments that are sensitive to stochastic flight delays. The framework includes three components, a stochastic gate assignment model, a real-time assignment rule, and two penalty adjustment methods. The test results are based on data supplied by a Taiwan international airport, and show that the proposed framework performs better than the current manual assignment process and the traditional deterministic model.     

内增强变象管相机中的干扰研究

本文讨论了带快门的内增强变象管相机的快门电路及其对扫描电路的干扰,干扰信号对相机性能指标的影响及解决方法。     

Influence of postdeposition annealing on structural properties and electrical characteristics of thin Tm2O3 and Tm2Ti2O7 dielectrics

We describe the structural properties and electrical characteristics of thin thulium oxide (Tm₂O₃) and thulium titanium oxide (Tm₂Ti₂O₇) as gate dielectrics deposited on silicon substrates through reactive sputtering. The structural and morphological features of these films were explored by X-ray diffraction, X-ray photoelectron spectroscopy, secondary ion mass spectrometry, and atomic force microscopy, measurements. It is found that the Tm₂Ti₂O₇ film annealed at 800 °C exhibited a thinner capacitance equivalent thickness of 19.8 Å, a lower interface trap density of 8.37 × 10¹¹ eV⁻¹ cm⁻², and a smaller hysteresis voltage of ∼4 mV than the other conditions. We attribute this behavior to the Ti incorporated into the Tm₂O₃ film improving the interfacial layer and the surface roughness. This film also shows negligible degrees of charge trapping at high electric field stress.     

场发射栅孔阵列的制备

 采用硅的局部氧化技术以及湿法刻蚀技术,利用2.6 μm的光刻掩模板在n型硅片上形成了栅极孔径为1 μm的场发射阴极的栅极空腔阵列,实现了用大阵点尺寸的栅极掩模板制备较小尺寸栅孔阵列。硅的湿法刻蚀溶液采用各向同性的硝酸和氢氟酸混合溶液,刻蚀后空腔的深度和宽度均随刻蚀时间线性增加。同时,由于刻蚀溶液具有较高的Si/SiO₂ 刻蚀选择比,栅极孔径随刻蚀时间增大的速度远低于深度和宽度增大的速度,栅极孔径主要取决于掩模的尺寸和氧化层的厚度。通过选择掩模板的尺寸以及氧化层的厚度,采用局部氧化技术和湿法刻蚀技术能够制备出微米或亚微米的场发射阴极的栅极空腔阵列。     

采集强干扰下微弱信号的APD电路系统研究

基于雪崩光电二极管反向偏压及其电容特性,利用时间同步原理,构建了一个用于回避强烈反射光信号,探测微弱回波信号的雪崩光电二极管探测系统.对雪崩光电二极管电容效应作出了分析,得出交流高压供电会使雪崩光电二极管产生干扰尖峰脉冲的结论.为了消除这个电容效应产生的尖峰干扰,提出了施加直流反向低压的方案,以达到减少雪崩光电二极管电容变化量的目的.通过实验数据验证了方法可行性.