Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

A novel nanoscale fin field effect transistor by amended channel: Investigation and fundamental physics

The present paper proposes a new Fin Field Effect Transistor (FinFET) with an amended Channel (AC). The fin region consists of two sections; the lower part which has a rounded shape and the upper part of fin as conventional FinFETs, is cubic. The AC-FinFET devices are proven to have a lower threshold voltage roll-off, reduced DIBL, better subthreshold slope characteristics, and a better gate capacitance in comparison with the C-FinFET. Moreover, the simulation result with three-dimensional and two-carrier device simulator demonstrates an improved output characteristic of the proposed structure due to reduction of self-heating effect. Due to the rounded shape of the lower fin region and decreasing corner effects there, the heat can flow easily, and the device temperature will decrease. Also the gate control over the channel increases due to the narrow upper part of the fin. The paper, thus, attempts to show the advantages of higher performance AC-FinFET device over the conventional one, and its effect on the operation of nanoscale devices.     

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.     

Breakdown mechanisms in AlGaN/GaN high electron mobility transistors with different GaN channel thickness values

In this paper,the off-state breakdown characteristics of two different AlGaN/GaN high electron mobility transistors（HEMTs）,featuring a 50-nm and a 150-nm GaN thick channel layer,respectively,are compared.The HEMT with a thick channel exhibits a little larger pinch-off drain current but significantly enhanced off-state breakdown voltage(SV_off).Device simulation indicates that thickening the channel increases the drain-induced barrier lowering（DIBL） but reduces the lateral electric field in the channel and buffer underneath the gate.The increase of BV_off in the thick channel device is due to the reduction of the electric field.These results demonstrate that it is necessary to select an appropriate channel thickness to balance DIBL and BV_off in AlGaN/GaN HEMTs.     

新型SOANN埋层SOI器件的自加热效应研究

本文提出了一个新型的SOI埋层结构SOANN (silicon on aluminum nitride with nothing),用AlN代替传统的SiO₂材料,并在SOI埋氧化层中引入空洞散热通道. 分析了新结构SOI器件的自加热效应.研究结果表明:用AlN做为SOI埋氧化层的材料, 降低了晶格温度,有效抑制了自加热效应.埋氧化层中的空洞,可以进一步提供散热通道, 使埋氧化层的介电常数下降,减小了电力线从漏端通过埋氧到源端的耦合, 有效抑制了漏致势垒降低DIBL(drain Induced barrier lowering)效应.因此,本文提出的新型SOANN结构可以提高SOI器件的整体性能,具有优良的可靠性.     

Corner effects in double-gate/gate-all-around MOSFETs

Two kinds of corner effects existing in double-gate (DG) and gate-all-around (GAA) MOSFETs have been investigated by three-dimensional (3D) and two-dimensional (2D) simulations. It is found that the corner effect caused by conterminous gates, which is usually deemed to deteriorate the transistor performance, does not always play a negative role in GAA transistors. It can suppress the leakage current of transistors with low channel doping, though it will enhance the leakage current at high channel doping. The study of another kind of corner effect, which exists in the corner at the bottom of the silicon pillar of DG/GAA vertical MOSFETs, indicates that the D-top structure with drain on the top of the device pillar of vertical transistor shows great advantage due to lower leakage current and better DIBL (drain induced barrier lowering) effect immunity than the S-top structure with source on the top of the device pillar. Therefore the D-top structure is more suitable when the requirement in leakage current and short channel character is critical.