Design and practical implementation of multifrequency RF front ends using direct RF sampling

The use of direct RF sampling has been explored as a means of designing multifrequency RF front ends. Such front ends will be useful to multifrequency RF applications such as global navigation satellite system receivers that use global positioning system (GPS) L1, L2, and L5 signals and Galileo signals. The design of a practical multifrequency direct RF sampling front end is dependent on having an analog-to-digital converter whose input bandwidth accommodates the highest carrier frequency and whose maximum sampling frequency is more than twice the cumulative bandwidth about the multiple carrier signals. The principle of direct RF sampling is used to alias all frequency bands of interest onto portions of the Nyquist bandwidth that do not overlap. This paper presents a new algorithm that finds the minimum sampling frequency that avoids overlap. This design approach requires a multifrequency bandpass filter for the frequency bands of interest. A prototype front end has been designed, built, and tested. It receives a GPS coarse/acquisition code at the L1 frequency and GPS antispoofing precision code at both L1 and L2. Dual-frequency signals with received carrier-to-noise ratios in excess of 52 dB-Hz have been acquired and tracked using this system.     

Bit-wise parallel algorithms for efficient software correlation applied to a GPS software receiver

A set of efficient algorithms for processing code-division multiple-access spread spectrum signals has been developed. They make use of bit-wise parallelism to process 32 samples simultaneously. These algorithms have been implemented in a real-time global positioning system software receiver. The receiver consists of a radio-frequency front end, a system of shift registers, a digital data acquisition card, and software that runs on a 1.73-GHz PC. The PC performs base-band mixing and pseudorandom noise code correlations in a manner that directly simulates a hardware digital correlator.     

Augmented lagrangian nonlinear programming algorithm that uses SQP and trust region techniques

An augmented Lagrangian nonlinear programming algorithm has been developed. Its goals are to achieve robust global convergence and fast local convergence. Several unique strategies help the algorithm achieve these dual goals. The algorithm consists of three nested loops. The outer loop estimates the Kuhn-Tucker multipliers at a rapid linear rate of convergence. The middle loop minimizes the augmented Lagrangian functions for fixed multipliers. This loop uses the sequential quadratic programming technique with a box trust region stepsize restriction. The inner loop solves a single quadratic program. Slack variables and a constrained form of the fixed-multiplier middleloop problem work together with curved line searches in the inner-loop problem to allow large penalty wieghts for rapid outer-loop convergence. The inner-loop quadratic programs include quadratic onstraint terms, which complicate the inner loop, but speed the middle-loop progress when the constraint curvature is large.The new algorithm compares favorably with a commercial sequential quadratic programming algorithm on five low-order test problems. Its convergence is more robust, and its speed is not much slower.This research was supported in part by the National Aeronautics and Space Administration under Grant No. NAG-1-1009.     

Parallel orthogonal factorization null-space method for dynamic quadratic programming

An algorithm has been developed to solve quadratic programs that have a dynamic programming structure. It has been developed for use as part of a parallel trajectory optimization algorithm and aims to achieve significant speed without sacrificing numerical stability. the algorithm makes use of the dynamic programming problem structure and the domain decomposition approach. It parallelizes the orthogonal factorization null-space method of quadratic programming by developing a parallel orthogonal factorization and a parallel Cholesky factorization. Tests of the algorithm on a 32-node INTEL iPSC/2 hypercube demonstrate speedup factors as large as 10 in comparison to the fastest known equivalent serial algorithm.This research was supported in part by the National Aeronautics and Space Administration under Grant No. NAG-1-1009.     

Real-time generation of bit-wise parallel representations of over-sampled PRN codes

An algorithm has been developed that maps pseudo-random number codes onto a set of sample times and stores the results in a bit-wise parallel format. It allows bit-wise parallel software correlation of code-division multiple-access signals to be carried out using long pseudo-random number codes. Bit-wise parallel algorithms speed up software correlation by operating in parallel on multiple samples. The new algorithm uses table look-ups to over-sample a pseudo-random number code. It reduces the PRN code memory requirements of a GPS software receiver by a factor of 3.8 or more, maintains operational efficiency, and keeps code distortion low.     

Parallel solver for trajectory optimization search directions

A key algorithmic element of a real-time trajectory optimization hardware/software implementation is presented, the search step solver. This is one piece of an algorithm whose overall goal is to make nonlinear trajectory optimization fast enough to provide real-time commands during guidance of a vehicle such as an aeromaneuvering orbiter or the National Aerospace Plane. Many methods of nonlinear programming require the solution of a quadratic program (QP) at each iteration to determine the search step. In the trajectory optimization case, the QP has a special dynamic programming structure, an LQR-like structure. The algorithm exploits this special structure with a divide-and-conquer type of parallel implementation. A hypercube message-passing parallel machine, the INTEL iPSC/2, has been used. The algorithm solves a (p·N)-stage problem onN processors inO(p + log₂ N) operations. The algorithm yields a factor of 8 speed-up over the fastest known serial algorithm when solving a 1024-stage test problem on 32 processors.This research was supported in part by the National Aeronautics and Space Administration under Grant No. NAG-1-1009.