Ultrafast solvation dynamics of human serum albumin: correlations with conformational transitions and site-selected recognition

Human serum albumin, the most abundant protein found in blood plasma, transports a great variety of ligands in the circulatory system and undergoes reversible conformational transitions over a wide range of pH values. We report here our systematic studies of solvation dynamics and local rigidity in these conformations using a single intrinsic tryptophan (W214) residue as a local molecular probe. With femtosecond resolution, we observed a robust bimodal distribution of time scales for all conformational isomers. The initial solvation occurs in several picoseconds, representing the local librational/rotational motions, followed by the dynamics, in the tens to hundreds of picoseconds, which result from the more bonded water in the tryptophan crevice. Under the physiological condition of neutral pH, we measured approximately 100 ps for the decay of the solvation correlation function and observed a large wobbling motion at the binding site that is deeply buried in a crevice, revealing the softness of the binding pocket and the large plasticity of the native structure. At acidic pH, the albumin molecule transforms to an extended conformation with a large charge distribution at the surface, and a similar temporal behavior was observed. However, at the basic pH, the protein opens the crevice and tightens its globular structure, and we observed significantly faster dynamics, 25-45 ps. These changes in the solvation dynamics are correlated with the conformational transitions and related to their structural integrity.     

Optimal design of a dual-oxide nano-CMOS universal level converter for multi-V dd SoCs

Multiple supply voltage based (V _dd ) Systems on Chip (SoCs) allow designers to implement large, complex systems for diverse applications. However, the need for level conversion imposes penalties and often results in non-optimal SoCs. Thus, the level converters are overhead for the circuits in which they are being used. If power consumption of the level converters continues to grow, then they will fail to serve the very purpose for which they were built. This paper proposes the power (leakage)-delay optimization of a DC to DC universal voltage level converter (ULC) using a dual-T _ox (dual-oxide CMOS or DOXCMOS) technique and exploiting transistor geometry. The proposed ULC is a novel circuit proposed here for the first time and performs level-up, level-down conversion, or blocking of the input signal, based on the requirements. The paper further proposes a novel design methodology accompanied by an optimization algorithm for the parasitic-aware power-delay optimization of the ULC circuit. The entire design has been implemented in 90?nm CMOS up to layout, including DRC/LVS and parasitic (RC) re-simulation, and was subjected to process variation of 10 process parameters. The optimal ULC with 20 transistors yields power savings of 87.5 %, delay improvement of 87.3 % and area savings of 21?% over the baseline design. It is a robust design performing a stable voltage level conversion for voltages as low as 0.6?V (50 % of V _dd ) and loads varying from 10 to 200 fF.