Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity

To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown.     

Size Effect on Properties of Varistors Made From Zinc Oxide Nanoparticles Through Low Temperature Spark Plasma Sintering

Conditions for the elaboration of nanostructured varistors by spark plasma sintering (SPS) are investigated, using 8‐nm zinc oxide nanoparticles synthesized following an organometallic approach. A binary system constituted of zinc oxide and bismuth oxide nanoparticles is used for this purpose. It is synthesized at room temperature in an organic solution through the hydrolysis of dicyclohexylzinc and bismuth acetate precursors. Sintering of this material is performed by SPS at various temperatures and dwell times. The determination of the microstructure and the chemical composition of the as‐prepared ceramics are based on scanning electron microscopy and X‐ray diffraction analysis. The nonlinear electrical characteristics are evidenced by current–voltage measurements. The breakdown voltage of these nanostructured varistors strongly depends on grain sizes. The results show that nanostructured varistors are obtained by SPS at sintering temperatures ranging from 550 to 600 °C.     

Current mismatch due to local dopant fluctuations in MOSFET channel

A microscopic multitransistor model is developed to analyze the impact of local dopant fluctuation on the intrinsic mismatch of long-channel MOSFET. A closed analytical formula for current mismatch is derived to show a nonscaled and self-consistent form /spl sim/[4+Log(L/L/sub min/)]/WL. This is in contrast to the global fluctuation model, in which the current mismatch has a universal scaling form /spl sim/1/WL but is not self-consistent if a MOSFET is modeled as an equivalent two-transistor system. The weak violation of scaling law results from the local fluctuation that has more impact on longer channel devices than on shorter ones. Our new model is consistent with recent experimental observation and can explain the discrepancies between the experimental data and the existing models. The analysis indicates that the local dopant fluctuation is the major cause and accounts for about 60% to 80% of total current mismatch when operated at lower gate voltage, a usual regime for higher output impedance.     

Application of a floating well concept to a latch-up-free,low-cost, smart power high-side switch technology

An original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology is presented. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up     

Cost-effective smart power CMOS/DMOS technology: design of main driving and protection functions

This paper intends to show that even with a CMOS technology main driving and protection functions of a power VDMOS can be made performant. Original circuits taking advantage of the availibility of the parasitic vertical bipolar transistor are presented and experimentally evaluated. A current mode approach is proposed to improve the accuracy of the current sensing function aimed at performing overcurrent, short-circuit and open-load detection.