A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7μm CMOS ASIC

A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 μm to 0.3 μm. The chip is 0.9×3.4 mm² using 0.3 μm rules     

60Co γ-ray induced gain degradation in bipolar junction transistors

Commercial indigenously made npn and pnp bipolar junction switching transistors used for space applications are investigated for ⁶⁰Co γ-ray induced effects. The on-line as well as off-line measurements indicate that the forward current gain of the transistors decreases significantly as the accumulated dose increases. Excess base current model is employed to account for the current gain degradation. The pnp transistor undergoes as much degradation as the npn type. It is found that bulk degradation by displacement damage is the dominant mechanism leading to reduction in forward current gain of npn transistors. On the other hand it appears that, in addition to bulk damage, surface degradation due to accumulation of interface states at the silicon-silicon dioxide interface also contributes significantly to gain degradation in pnp transistor as evident from thermal annealing studies. Further, estimation reveals that the transistor with larger base width has higher displacement damage factor.