一种8-b 180KSPS的带有新颖的时域比较器且有效位数7.97的差分逐次逼近模数转换器

This paper presents a differential successive approximation register analog-to-digital converter (SAR ADC) with a novel time-domain comparator design for wireless sensor networks. The prototype chip has been implemented in the UMC 0.18-μ m 1P6M CMOS process. The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz. With the Nyquist input frequency, 68.49-dB SFDR, 7.97-ENOB is achieved. A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout. The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.     

应用于流水线模数转换器的鲁棒且简易的双模式数字校正技术

This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters (ADC).The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom(PN) sequence injection capacitors at the ADC initialization,while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation.The presented technique not only reduces the complexity of analog circuit by eliminating the...     

An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB

This paper presents a differential successive approximation register analog-to-digital converter(SAR ADC) with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process.The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz.With the Nyquist input frequency,68.49-dB SFDR,7.97-ENOB is achieved.A simple quadrate layout is adopted to ease the routing complexity of the co...     

A robust and simple two-mode digital calibration technique for pipelined ADC

This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters (ADC).The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom(PN) sequence injection capacitors at the ADC initialization,while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation.The presented technique not only reduces the complexity of analog circuit by eliminating the implementation of PN sequence with accurate amplitude in analog domain,but also improves the performance of digital background calibration by minimizing the sensitivity of calibration accuracy to sub-ADC errors.The use of opamps with low DC gains in normal operation makes the proposed design more compatible with future nanometer CMOS technology.The prototype of a 12-bit 40-MS/s pipelined ADC with the two-mode digital calibration is implemented in 0.18-μm CMOS process.Adopting a simple telescopic opamp with a DC gain of 58-dB in the first stage,the measured SFDR and SNDR within the first Nyquist zone reach 80-dB and 66-dB,respectively.With the calibration,the maximum integral nonlinearity (INL) of the ADC reduces from 4.75-LSB to 0.65-LSB,while the ADC core consumes 82-mW at 3.3-V power supply.