Novel level-identifying circuit for flash multilevel memories

This paper presents a high-speed, small-area circuit specifically designed to identify the levels in the read out operation of a flash multilevel memory. The circuit is based on the analog computation of the Euclidean distance between the current read out from a memory cell and the reference currents that represent the different logic levels. An experimental version of the circuit has been integrated in a standard double-metal 0.7-μm CMOS process with a die area of only 140×100 μm². Operating under a 5-V power supply, this circuit identifies the read-out current of a memory cell, and associates it with the appropriate logic level in 9 ns     

An easy-to-use mismatch model for the MOS transistor

In this paper, a physics-based mismatch model is presented. It is demonstrated on a 0.18-/spl mu/m technology that a simple mismatch model can still be used to characterize deep-submicron technologies. The accuracy of the model is examined and found to be within 20% in the strong inversion region. Bulk bias dependence is modeled in a physical way. To extract the mismatch parameters, a weighted fit is introduced. It is shown that the width and length dependence of the mismatch parameters is given by the Pelgrom model.     

Strategy and issue frames in election campaign coverage: a social cognitive account of framing effects

This study examines how news frames in campaign coverage affect individuals' interpretation of campaigns. Framing effects are conceptualized in terms of the process by which textual features in news stories set limits on knowledge use in the construction of a discourse model - a mental model constructed through the interaction between news frames and the interpreter's social knowledge. Examining message structures in campaign news stories led to identifying two major frames in campaign coverage: strategy and issue. Narrative data collected from two field experiments were analyzed. The findings suggest that both strategy-framed and issue-framed print news stories are effective in influencing campaign interpretation.     

Parameter extraction on MOSFET transistors using a new optimised fit strategy

Classical parameter-extraction programs rely on the minimisation of the relative current deviation. However, since, especially for analogue applications, the slope of the IDS/VDS curve in the saturation region is at least equally important, a new fit strategy has been developed. This new fit strategy extracts a parameter set which optimises the current residual as well as the slope residual at every point.     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

Implementation of an integrated glucose POCT system

In response to a change of the Belgian National Directives whereby hospital laboratories became responsible for all point-of-care testing (POCT) performed within hospital walls a standardized and automated POC glucose-testing system was implemented in our hospital. The system consists of 50 AccuCheck Inform instruments (Roche Diagnostics, Vilvoorde, Belgium), 50 docking stations, a DataCare Server, and connections to the medical laboratory information system (MOLIS, Sysmex, Barchon, Belgium) and to the hospital information system. Implementation involved many parties and extensive preparation and communication. Key issues were bar-coded patient and user identification, training, and responsibilities. One year after the hospital wide implementation of this system the quality of POC glucose testing has significantly increased, thereby improving patient safety. This study describes a stepwise change over involving the medical laboratory and with a focus on hands-on quality.Presented at the ninth conference on Quality in the Spotlight, 18–19 March 2004, Antwerp, Belgium.     

Derivatization of 1-phenyl substituted 4-amino-2-benzazepin-3-ones: evaluation of Pd-catalyzed coupling reactions

Several Pd-catalyzed reactions were explored to further functionalize the bromo-substituted 4-amino-1,2,4,5-tetrahydro-2-benzazepin-3-one scaffold (Aba). We report in this paper suitable reaction conditions for Suzuki, Buchwald-Hartwig, and Heck reactions. The substitution pattern of the starting aminobenzazepinone turned out to be crucial for the success of these transition metal-catalyzed reactions, which often required modifications of standard literature procedures. The Pd-catalyzed methods provide access to novel substitution patterns of the Aba scaffold.     

Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

On the hot-carrier-induced post-stress interface trap generation inn-channel MOS transistors

A continued fast interface trap generation is observed in n-channel MOS transistors after termination of the hot-carrier stress. The magnitude of this post-stress effect is strongly dependent on the conditions of the preceding stress, on the post-stress conditions and on the process parameters. For measurements at 293 K, a simple model is proposed which is based on the release of hydrogen by the thermal detrapping of holes, and which can explain the observed dependencies. The importance of the post-stress D_it-generation is illustrated for the case of dynamic stress conditions where it can lead to an apparently deviating degradation behavior