Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity

To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown.     

Application of a floating well concept to a latch-up-free,low-cost, smart power high-side switch technology

An original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology is presented. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up     

Design and applications of an easily integrable CMOS operational floating amplifier for the MegaHertz range

The design and major applications of a general purpose current mode building block are presented in this paper. This circuit is basically a high gain transconductance scheme with differential current output terminals previously termed operational floating amplifier (OFA). The novel structure proposed here is shown to implement a very flexible and high performance amplifier which can be used in almost all applications employing conveyors, current feedback amplifiers or even conventional operational amplifiers with improved performance characteristics. This presentation is also supported by experimental measurements on a prototype circuit realized in CMOS technology.     

Cost-effective smart power CMOS/DMOS technology: design of main driving and protection functions

This paper intends to show that even with a CMOS technology main driving and protection functions of a power VDMOS can be made performant. Original circuits taking advantage of the availibility of the parasitic vertical bipolar transistor are presented and experimentally evaluated. A current mode approach is proposed to improve the accuracy of the current sensing function aimed at performing overcurrent, short-circuit and open-load detection.     

The mirrored lateral SCR (MILSCR) as an ESD protection structure:design and optimization using 2-D device simulation

A methodology for the application of two-dimensional (2-D) device simulation to electrostatic discharge (ESD) events is presented. Correlation of ESD simulation results with experimental data is illustrated using a grounded base n-p-n transistor. It is shown that device simulation is essential for understanding complex ESD failure mechanisms. The application of the methodology to the design of a new ESD protection structure, the mirrored lateral silicon controlled rectifier (MILSCR), is then discussed. Experimental results show that the MILSCR provides a very efficient double-polarity ESD protection. Finally, device simulation is used to optimize this structure for smart-power applications. In particular, holding currents as high as 134 mA are achieved, allowing one to cope with the latchup danger during normal operation