模块化基带设计——实现低成本和可再用无线架构

数月前,我曾发表过一篇关于模块化基站设计的文章(刊登于本刊2006年4月期),阐述下一代基带系统理想架构中的关键元件。文章回顾了通用公共无线电接口(CPRI)、开放式基站架构发起组织(OBSAI)、先进电信计算架构(A T C A)和串行RapidIO等标准对于下一代系统的重要性。同时,文章还     

Natural and artificial radioactivity levels of greenhouse soils and relations with soil properties

Journal of Radioanalytical and Nuclear Chemistry - In this study, natural (226Ra, 232Th, 40K) and artificial (137Cs) radionuclide activity concentration levels of 63 greenhouse soils collected from...     

Effects of temperature on series resistance determination of electrodeposited Cr/n-Si/Au-Sb Schottky structures

Temperature dependences of the series resistance in the Cr/n-Si/Au-Sb Schottky structures prepared by electrodeposition method have been studied using current-voltage (I-V) characteristics in the 80-320 K temperature range by steps of 20 K. However, the values of series resistance obtained from Cheung functions were compared with each other, and it was seen that there is a good agreement between the values of the series resistance. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height and the series resistance. The barrier height and series resistance obtained from Norde’s function were compared with those from Cheung functions. The values of barrier height and series resistance have very different especially towards to the lower temperatures. This is attributed to non-ideal I-V characteristics of the Cr/n-Si/Au-Sb Schottky structure and non-pure thermionic emission theory due to the low temperature effects.     

Combined Linear and $Delta$-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters

A combined linear and delta-modulated (DeltaM) switch-mode PA supply modulator for polar transmitters in wireless handsets is designed in a 0.25 mum CMOS process. The modulator employs a DeltaM switch-mode DC-DC buck converter to enhance the efficiency of a linear regulator at backed-off supply voltages and powers. The delta-modulator's noise-shaping characteristic, linear regulator's power supply rejection, digital pre-emphasis of the input envelope, and a closed-loop amplitude path from the PA output are simultaneously used to achieve state-of-the-art modulator performance. The presented supply modulator follows the input signal's envelope with 20 dB output dynamic range, maximum efficiency of 75.5% at an output power of 30.8 dBm, and 75 dB SFDR for envelope signals up to 4 MHz occupied RF bandwidth. For a 1625 kb/s 8 PSK RF input signal at 900 MHz, polar modulation of a commercial low-power GSM-900 PA provides 10 dB ACPR improvement.     

0–30?V common mode range, 120?dB CMRR, and 10?nV/ \sqrt {\text{Hz}} noise floor current shunt monitor IC with an embedded ΣΔ modulated digital interface

Sensing and controlling current flow is a fundamental requirement for many electronic systems, including power management (DC?CDC converters and LDOs), battery chargers, electric vehicles, solenoid positioning, motor control, and power monitoring. Current shunt monitor (CSM) system enables current measurement across an external sense resistor (R _S ) in series to current flow. Proposed CSM system can sense a system (power supply) current from 1 to 500?mA across a typical board Cu-trace resistance of 1??? with less than 10???V input-referred offset, 150?nV/°C offset drift and 0.1% accuracy. Instead of using a costly zero-TC sense resistor (R _S ) that is used in typical CSM systems; proposed method uses existing Cu board trace for sensing. The sense amplifier uses chopper stabilization in the signal chain of the amplifier to suppress input-referred offset down to less than 10???V. Switching current-mode (SI) FIR filtering is used at the instrumentation amplifier output to filter out the chopping ripple at the harmonics of the chopping frequency. A frequency domain Sigma Delta (????FD) ADC enables a digital interface to processor applications. The CSM is fabricated on a 0.7???m CMOS process with three levels of metal with maximum Vds tolerance of 8?V, and operates across a common mode range of 0?C30?V achieving less than 10?nV/ $ \sqrt {\text{Hz}} $ of flicker noise at 100?Hz. By using a semi-digital SI FIR filter, residual chopper ripple is suppressed by more than 7.5?mV_pp from the base line of 8?mV_pp, which is equivalent to 25?dB suppression.     

DisplayPort在电视中的应用

DisplayPort是视频电子标准协会(Video Electronic Standards Association-VESA)新的接口标准,简化了显示设计及其相关的连接.它还以强大的电气特性支持更高的分辨率.虽然从目前的应用来看,DisplayPort接口主要应用于笔记本和显示器,但其也适用于数字电视等很多嵌入式和内部应用.     

A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With −75 dBc Single-Tone Sensitivity at 100 kHz Offset

An on-chip clock phase-noise measurement circuit is presented. Unlike previously reported monolithic measurement techniques that measure jitter in the time domain, the proposed module measures the phase-noise spectrum. The proposed circuit is fully integrated and does not require a spectrally clean reference clock or any external calibration. The module can be integrated as part of a built-in self-test (BIST) scheme for PLL clock synthesizers. The proposed circuit uses a low-noise voltage-controlled delay-line (VCDL) and mixer-based frequency discriminator to extract the phase-noise fluctuations at baseband. A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point. The proposed circuit is fabricated using a 0.25 mum digital CMOS process and operates up to a 2 GHz carrier frequency. It achieves a single-tone measurement sensitivity of -75 dBc and an equivalent phase-noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.     

Impact of Sampling Clock Phase Noise on Σ∆ Frequency Discriminators

SigmaDelta frequency discriminators (SigmaDeltaFDs) convert instantaneous frequency deviations of a carrier signal to digital. They are used for decoding narrowband phase or frequency modulated signals in communication receivers, self calibration of RF frequency synthesizers and in digital phase locked loops. In this paper, the impact of reference (sampling) clock phase noise on a SigmaDeltaFD's spurious-free dynamic range (SFDR) is derived. It is shown that for SigmaDeltaFDs with jittered sampling clock, in addition to FM sidebands, a high baseband tonal content is generated degrading overall SFDR. The reference clock phase noise impact is derived mathematically, and two commonly used SigmaDeltaFDs circuits are designed and implemented to verify the results experimentally. Experimental results are shown to match the theoretical prediction of SFDR within 3 dB.     

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.     

A low noise,high power efficiency supply regulator for near-field power delivery

In order to deliver near-field electromagnetic power to a biomedical device or an RFID tag efficiently, the downlink signal is preferred to be at a high voltage level. To reduce power consumption and meet low supply requirements, it is advantageous for the remote device power supply to step-down the input voltage following rectification, typically using switch-mode regulators. The output ripple of a switched capacitor converter is inversely proportional to the filtering capacitance at the output node and switching frequency. In this paper, a hybrid DC–DC converter utilizing a switched capacitor regulator in master–slave configuration with a linear regulator is presented. Linear regulator actively cancels the switching ripple, while low frequency and DC current is provided by the switched capacitor converter. The converter is designed to receive an average input voltage of 5 Vpk from the receiver coil, with an output voltage of 2 V, and 5 mA of output current. The proposed regulator is fabricated in 0.35 μm technology. The power efficiency is measured to be 67%, with a nominal peak to peak ripple of less than 2 mV at the output.