应用于WLAN系统具有高线性度的基带Gm-C滤波器

本文介绍了一种应用于无线局域网(WLAN)收发机系统的跨导-电容(Gm-C)低通滤波器,该滤波器能够工作于低电压并具有高线性度。该射频发射器(Tx)中的滤波器采用截止频率为9.8MHz的三阶切比雪夫低通滤波器原形,在30MHz频率处的阻带衰减达到35dB。由于采用了工作在线性区MOS的伪差分跨导,此滤波器的IIP3可达9.5dBm之高。本电路采用0.35-μm CMOS工艺实现,滤波器的芯片面积为0.41mm0.17mm,工作在3.3V电源电压时所消耗电流为3.36mA 。     

A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

This paper presents a 200mA low-dropout (LDO) linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier using common source stage with variable load, which is controlled by output current, is served as the second stage for stable frequency responses. Another technique is the LDO uses pole-zero tracking compensation technique at error amplifier to achieve good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8V-5V and provides up to 200mA load current for an output voltage of 1.8V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630*550μm² and the quiescent current is 130μA.     

一种应用于直接变频系统的低功耗混合信号直流失调消除电路

A low power mixed signal DC offset calibration (DCOC) circuit for direct conversion receiver applications is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 × 0.419 mm².     

一种应用于IEEE 802.11 b/g/n无线局域网收发机的CMOS模拟基带电路

本文提出了一种应用于直接变频无线局域网收发机的模拟基带电路,该电路采用标准的0.13微米CMOS工艺实现,包括了采用有源RC方式实现的接收4阶椭圆低通滤波器、发射3阶切比雪夫低通滤波器、包含直流失调消除伺服环路的接收可变增益放大器及片上输出缓冲器。芯片面积共1.26平方毫米。接收基带链路增益可在-11dB至49dB间以2dB步长调节。相应地,基带接收输入等效噪声电压（IRN）在50 nV/sqrt(Hz) 至30.2 nV/ sqrt(Hz)间变化而带内输入三阶交调（IIP3）在21dBm至-41dBm间变化。接收及发射低通滤波器的转折频率可在5MHz、10MHz及20MHz之间选择以符合包含802.11b/g/n的多种标准的要求。接收基带I、Q两路的增益可在-1.6dB至0.9dB之间以0.1dB的步长分别调节以实现发射IQ增益失调校正。通过采用基于相同积分器的椭圆滤波器综合技术及作用于电容阵列的全局补偿技术,接收滤波器的功耗显著降低。工作于1.2V电源电压时,整个芯片的基带接收及发射链路分别消耗26.8mA及8mA电流。     

调频电视系统干扰效应的实验研究

通过主观测量和客观测量研究了单频、数字调制信号和雷达信号对调频电视系统的干扰效应。在此基础上,得出了干扰噪声功率的加权网络与加权函数,最后,给出了利用这些加权函数和文献[2]中导出的公式估算防护比的方法。估算值与主观测量符合较好,表明这种估算方法是可靠的。     

一种应用于CMMB调谐器芯片的低功耗八阶椭圆低通滤波器

本文提出了一种应用于中国移动多媒体广播（CMMB）调谐器芯片的八阶有源RC椭圆低通滤波器（LPF）电路,其-3分贝转折频率（f-3dB）为1兆或4兆赫兹。滤波器的运算放大器（Op-Amps）设计采用了一种新颖的增益带宽积扩展技术,在实现滤波器两倍转折频率处71分贝的阻带衰减从而满足了CMMB标准所要求的高邻频抑制（ACR）的同时,单个通道工作于3伏电压时仅消耗2.8毫安电流,近一步减小滤波器的偏置电流至2毫安/通道时,测得其幅频响应在通带边缘的凸起仅为0.5分贝。滤波器的运算放大器还采用了经过优化的共模控制电路,使得在增加其共模抑制比（CMRR）的同时还能够有效抑制共模大信号干扰。测试结果表明滤波器的带内输入三阶交调点为128dBμVrms,带内共模抑制比大于80分贝。本文所提出的滤波器采用0.35微米锗硅BiCMOS工艺实现,芯片总面积为1.19平方毫米。     

A highly linear baseband G_m-C filter for WLAN application

A low voltage,highly linear transconductance-C（G_m-C） low-pass filter for wireless local area network （WLAN） transceiver application is proposed.This transmitter（Tx） filter adopts a 9.8 MHz 3rd-order Chebyshev low pass prototype and achieves 35 dB stop-band attenuation at 30 MHz frequency.By utilizing pseudo-differential linear-region MOS transconductors,the filter IIP₃ is measured to be as high as 9.5 dBm.Fabricated in a 0.35μm standard CMOS technology,the proposed filter chip occupies a 0.41×0.17 mm² die area and consumes 3.36 mA from a 3.3-V power supply.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

This paper presents a 200 mA low-dropout(LDO) linear regulator using two modified techniques for frequency compensation.One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current,is served as the second stage for a stable frequency response.The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response.The proposed circuit was fabricated and tested in HJTC 0.18μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8-5 V and provides up to 200 mA load current for an output voltage of 1.8 V.The total error of the output voltage due to line and load variation is less than 0.015%.The LDO die area is 630×550μm~2 and the quiescent current is 130μA.     

具有混合反馈的高Q和/或高fs开关电容带通滤波器

本文提出了一种减少电容分布和总电容的高Q和/或高f_s开关电容(SC)带通滤波器。在传统的双二次SC滤波器结构中,引入部分正反馈并改变前馈网络可使总电容和电容分布得到大幅度的减少。举例说明了二阶高Q(=50)SC带通滤波器设计,并比较了不同滤波器结构的性能参数。