X 波段氮化镓合成固态放大器

Based on a self-developed A1GaN/GaN HEMT with 2.5 mm gate width technology on a SiC substrate, an X-band GaN combined solid-state power amplifier module is fabricated. The module consists of an AIGaN/GaN HEMT, Wilkinson power couplers, DC-bias circuit and microstrip line. For each amplifier, we use a bipolar DC power source. Special RC networks at the input and output and a resistor between the DC power source and the gate of the transistor at the input are used for cancellation of self-oscillation and crosstalk of low-frequency of each amplifier. At the same time, branches of length 3λ/4 for Wilkinson power couplers are designed for the elimination of self-oscillation of the two amplifiers. Microstrip stub lines are used for input matching and output matching. Under Vds = 27 V, Vgs = -4.0 V, CW operating conditions at 8 GHz, the amplifier module exhibits a line gain of 5.6 dB with power added efficiency of 23.4%, and output power of 41.46 dBm （14 W）, and the power gain compression is 3 dB. Between 8 and 8.5 GHz, the variation of output power is less than 1.5 dB.     

超薄栅氧MOS器件传统关态栅泄漏电流研究

理论分析了MOSFET关态泄漏电流产生的物理机制,深入研究了栅氧化层厚度为1.4nm MOSFET传统关态下边缘直接隧穿栅泄漏现象.结果表明：边缘直接隧穿电流服从指数变化规律;传统关态下边缘直接隧穿对长沟道器件的影响大于短沟道器件;衬底反偏在一定程度上减小边缘直接隧穿泄漏电流.     

X波段四路合成氮化镓功率放大器

本文利用自主研制的SiC 衬底的,栅宽为2.5mm的AlGaN/GaN HEMT器件,设计完成了X波段氮化镓合成固态放大器模块。模块由AlGaN/GaN HEMT器件,Wilkinson功率合成/分配器,偏置电路和微带匹配电路构成。为了使放大器稳定,在每一路放大器的输入端和输出端加入了RC 稳定网络,在栅极和直流输入之间加上稳定电阻,并且利用3/4 λ 枝接的威尔金森功率合成/分配器,从而有效消除其自激和低频串扰问题。在连续波条件下(直流偏置电压为Vds=27V,Vgs=-4.0V),放大器在8GHz频率下线性增益为5dB,最大效率为17.9%,输出功率最大可为42.93dBm,此时放大器增益压缩为3dB。四路合成放大器的合成效率是67.5%。通过分析,发现了放大器合成效率的下降是由每路放大器特性的不一致、功率合成网络的损耗以及电路制造误差所造成。     

大尺寸电磁加热的氮化物MOCVD反应室温度场的仿真与优化

本文通过对电磁加热八英寸晶片的立式氮化物MOCVD反应室建立数学模型,利用有限元法,对传统的加热结构进行了优化.为提高晶片温度分布的均匀性,本文提出了矩形槽和圆环段形槽两种不同槽结构的基座,通过对这两种槽结构基座的优化分析发现,与传统用的基座相比,这两种槽结构的基座改变了传统基座中的传热方式和不同方向的传热速率,从而提高了晶片温度分布的均匀性,这有利于提高薄膜生长的质量.     

A面和C面AlGaN/GaN异质结的比较研究

采用MOCVD技术在R面和C面蓝宝石上生长非极性A面和极性C面AlGaN/GaN异质结。分别用X射线衍射仪和原子力显微镜比较了两种材料的结构特性及表面形貌,通过电容-电压测试比较了两种材料的电学特性。研究结果表明,较高浓度的二维电子气的存在使得极性材料在微波功率器件方面更有优势,而非极性材料可以消除与极化相关的电场,更适合应用于光电器件领域。     

GIDL应力下超薄栅氧LDD NMOS器件退化

The degradation of device under GIDL （gate-induced drain leakage current） stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC（stress induced leakage current）in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

SILC during NBTI Stress in PMOSFETs with Ultra-Thin SiON Gate Dielectrics

Negative bias temperature instability （NBTI） and stress-induced leakage current （SILC） both are more serious due to the aggressive scaling lowering of devices. We investigate the SILC during NBTI stress in PMOSFETs with ultra-thin gate dielectrics. The SILC sensed range from -1 V to 1 V is divided into four parts： the on-state SILC, the near-zero SILC, the off-state SILC sensed at lower positive voltages and the one sensed at higher positive voltages. We develop a model of tunnelling assisted by interface states and oxide bulk traps to explain the four different parts of SILC during NBTI stress.     

直接隧穿栅电流对CMOS逻辑电路的影响

对于纳米级的CMOS电路,由于MOS器件具有超薄的氧化层,栅隧穿漏电流的存在严重地影响了电路的正常工作。本文基于可靠性理论和电路级仿真深入地研究直接隧穿电流对CMOS逻辑电路的影响。仿真结果很好地与理论分析相符合,这些理论和仿真将有助于以后的集成电路设计。     

一种基于新型Precharge PFD的CMOS CPPLL设计

文章描述了一种基于新型无"过充"的边沿触发的鉴频鉴相器的CMOS电荷泵锁相环设计与仿真.电路设计基于UMC 2.5V 0.25μm CMOS工艺.Spice仿真结果显示,它可以实现快速锁定和较低的抖动性能.