可用于高密度高速度领域的一种新型两端静态存储单元的设计

A vertical two-terminal silicon PNPN diode is presented for use in a high-density memory cell. The device design for high-speed operations was studied with experiments and calibrated simulations, which proves that the proposed memory cell can be operated at nanosecond range. The static and dynamic power dissipations were also studied, which indicated the availability of the proposed memory cell for VLS1 applications. Moreover, the memory cell is compatible with CMOS process, has little impact from process variation, and has good reliability.     

含受弯根键的根式沉井承载性能分析

根据荷载传递法及Winkler地基梁理论,考虑根键弯曲及重叠折减效应,推导了含受弯根键的根式沉井承载性能的弹性解答,计算值在弹性范围内与实测值接近.给出了竖向位移和轴力随深度的分布曲线,并分析了根键的受力性状以及各部分土反力的分担比例等.结果表明,根式沉井的承载性能明显优于传统沉井基础,可应用于工程建设中,但根键的弯曲效应会降低基础的承载性能,故在设计中应提高根键的抗弯刚度.     

关于超薄埋氧层及超薄SOI的MOSFET器件衬底掺杂的设计研究

The importance of substrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide(ES-UB-MOSFETs) is demonstrated by simulation.A new substrate/backgate doping engineering,lateral non-uniform dopant distributions(LNDD) is investigated in ES-UB-MOSFETs.The effects of LNDD on device performance,V t-roll-off,channel mobility and random dopant fluctuation(RDF) are studied and optimized.Fixing the long channel threshold voltage(V t) at 0.3 V,ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm,meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length,which is 43% smaller.The LNDD degradation is 10% of the carrier mobility both for n MOS and p MOS,but it is canceled out by a good short channel effect controlled by the LNDD.Fixing V t at 0.3 V,in long channel devices,due to more channel doping concentration for the LNDD technique,the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs,but in the short channel,the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer.A novel process flow to form LNDD is proposed and simulated.     

可垂直集成的无电容式动态存储器件

A two-port capacitorless PNPN device with high density,high speed and low power memory fabricated using standard CMOS technology is presented.Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed(ns level),large read current margin(read current ratio of 10~4×),low process variation,good thermal reliability and available retention time(190 ms).Furthermore,the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.     

截止频率8.7 THz的平面肖特基势垒二极管

肖特基势垒二极管(SBD)具有强非线性效应、速度快及容易系统集成等特点,常用于微波、毫米波及太赫兹波的产生和检测。本文通过电子束光刻等技术制作出肖特基接触直径1 μm的二极管,并对二极管进行了直流测试和射频测试。经过直流测试,二极管的串联电阻为10.2 Ω,零偏结电容为1.76 fF,肖特基结截止频率达到了8.7 THz;相同管子的射频测试串联电阻为15.4 Ω,零偏结电容1.46 fF,肖特基结截止频率也达到了7 THz。     

刚性根式基础水平承载性能分析

根据Winkler地基梁理论, 分析根式基础及根键水平受力特性, 并建立计算模型. 利用 载荷传递法推导根式基础弹性解答, 计算其水平向承载性能, 获得井身位移、弯矩、剪力和 土反力随深度的分布规律. 结果表明, 根式基础承载性能优于沉井基础, 可使顶部水平位移 减少35%~45%, 承载力提高45%~55%. 载荷传递法结果在弹 性范围内与试验数据接近, 故可用于工程计算.