排序方式: 共有129条查询结果,搜索用时 484 毫秒
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CMOS折叠预放电路的失调是限制CMOS折叠结构A/D转换器实现高分辨率应用的主要原因之一.文中提出差分对的动态匹配技术改善了折叠预放电路的失调,从而为研制CMOS工艺中的高分辨率折叠结构A/D转换器提供了一种可行方案,并给出了MATLAB和电路仿真的实验结果. 相似文献
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为集成调谐器接收机芯片系统设计了一个带自动幅度控制回路的差分结构电容电感压控振荡器.通过采用pMOS管作为有源负阻使振荡器谐振回路可以直接接地电平,减小了寄生效应,扩大了频率调谐的线性及其范围.采用的自动幅度控制AAC回路具有元件少,噪声低,控制灵敏,调节容易,结构简单及设计方便的优点,并保证振荡器电路的性能最小地依赖于环境和制造工艺参数的变化.所设计的压控振荡器采用新加坡特许50GHz 0.35μm SiGe BiCMOS工艺流片,经测试在1MHz频率偏移处达到了-127.27dBc/Hz的相位噪声性能,具有宽的(990~1140MHz)和线性(调谐增益32.4MHz/V)的频率调谐曲线.整个振荡器电路在5V的供电电压下仅消耗6.6mA的电流,可以满足调谐器的应用需要. 相似文献
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The sample-and-hold (S/ H) circuit is a key module for many applications[1 ] totransform a continuous time signal into discrete one. In analog to digital (A/ D)converters,the front-end of the S/ H amplifier must be of both high speed... 相似文献
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This paper presents a 2.4 GHz power amplifier(PA) designed and implemented in 0.35μm SiGe BiCMOS technology.Instead of chip grounding through PCB vias,a metal plate with a mesa connecting ground is designed to decrease the parasitics in the PCB,improving the stability and the gain of the circuit.In addition,a low-pass network for output matching is designed to improve the linearity and power capability.At 2.4 GHz,a P_(1dB) of 15.7 dBm has been measured,and the small signal gain is 27.6 dB with S_(11)<-7 ... 相似文献
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正A sixth-order Butterworth Gm-C low-pass filter(LPF) with a continuous tuning architecture has been implemented for a wireless LAN(WLAN) transceiver in 0.35μm CMOS technology.An interior node scaling technique has been applied directly to the LPF to improve the dynamic range and the structure of the LPF has been optimized to reduce both the die size and the current consumption.Measurement results show that the filter has 77.5 dB dynamic range,16.3 ns group delay variation,better than 3%cutoff frequency accuracy,and 0 dBm passband IIP3.The whole LPF with the tuning circuit dissipates only 1.42 mA(5 MHz cutoff frequency) or 2.81 mA(10 MHz cutoff frequency) from 2.85 V supply voltage,and only occupies 0.175 mm~2 die size. 相似文献
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数控DC-DC变换器由于其自身的特点,易于与数字系统进行单片集成.DC-DC的数字控制算法有很多种,其中比较复杂的算法(如PID)需要在片内集成ADC,增加了设计难度.较为简单的控制方案只使用单一的比较器作为反馈输入部件,但动态性能较差.本文在已有的单比较器恒定步长反馈数控Buck转换器的基础上,提出了一类变步长反馈的方案.由于仍使用单比较器或窗口比较器,它的结构简单且易于集成.它借鉴了对分搜索的思路,能根据输出电压反馈的结果动态地改变占空比的变化步长,从而明显地提高了原有恒定步长反馈数控变换器的动态性能. 相似文献
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提出了一种采用单比较器变步长反馈控制和占空比抖动方法的数字DC- DC变换模块.它用6位二进制分辨率占空比的PWM信号实现了7位的电压分辨率.变步长反馈控制的使用使得它具有比恒定步长方案更好的动态性能,而且没有过多增加控制器的复杂度.在1MHz的开关频率下,控制器自身功耗小于0 .5 m W(不含功率开关及驱动部分) .由于电路的模拟部分极少,因此易与数字系统进行单芯片集成. 相似文献
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本文介绍了一种应用于无线局域网(WLAN)收发机系统的跨导-电容(Gm-C)低通滤波器,该滤波器能够工作于低电压并具有高线性度。该射频发射器(Tx)中的滤波器采用截止频率为9.8MHz的三阶切比雪夫低通滤波器原形,在30MHz频率处的阻带衰减达到35dB。由于采用了工作在线性区MOS的伪差分跨导,此滤波器的IIP3可达9.5dBm之高。本电路采用0.35-μm CMOS工艺实现,滤波器的芯片面积为0.41mm0.17mm,工作在3.3V电源电压时所消耗电流为3.36mA 。 相似文献
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A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network(WLAN) transceivers.A monolithic LC voltage controlled oscillator(VCO) is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping(MASH)△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm~2. 相似文献