体心立方金属中空位迁移规律

本文在考虑空位浓度对空位迁移能的影响和双空位效应的情况下,给出了体心立方金属中空位流与空位浓度梯度之间的定量关系。并指出当空位浓度超过一个临界值时,空位将向其浓度大的地方迁移。本文所用方法也可用于其它金属。 关键词：     

可用于高密度高速度领域的一种新型两端静态存储单元的设计

A vertical two-terminal silicon PNPN diode is presented for use in a high-density memory cell. The device design for high-speed operations was studied with experiments and calibrated simulations, which proves that the proposed memory cell can be operated at nanosecond range. The static and dynamic power dissipations were also studied, which indicated the availability of the proposed memory cell for VLS1 applications. Moreover, the memory cell is compatible with CMOS process, has little impact from process variation, and has good reliability.     

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

In the process of high-k films fabrication, a novel multi deposition multi annealing(MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing(PDA) times. The equivalent oxide thickness(EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore,the characteristics of SILC(stress-induced leakage current) for an ultra-thin SiO_2/HfO_2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.     

辐照材料的肿胀理论(Ⅱ) 偏吸率与肿胀公式

本文用分区的方法,得到了在同时计及位错应力场和辐照效应的情况下,位错周围点缺陷分布函数的零级、一级和二级近似解,进而得到了偏吸率。利用所得的偏吸率及文献[1]的结果,给出了新的肿胀公式。新公式优于前人的理论,不仅理论本身自洽,而且与实验符合较好。     

辐照材料的肿胀理论(Ⅰ)——中性尾闾

本文从反应扩散方程出发,研究在辐照条件下,微洞和位错(无应力场)周围点缺陷的分布情况。对含有点缺陷复合项的定态的反应扩散方程,给出了一种近似求解的方法并分别得到了微洞和位错吸收点缺陷的汇强度。从所得结果与前人略去复合项的结果比较可知,微洞较大时,复合项对汇强度的影响变得重要;对于位错,当点缺陷产生率较大时,考虑了复合项后所得的汇强度可达前人结果的1.5倍以上。 关键词：     

TiN/TaN 厚度变化对nMOSCAP栅叠层有效功函数的影响

We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the A1 diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.     

应用于三维集成的晶圆级键合技术

随着芯片集成度的不断提高以及CMOS工艺复杂度的增加,集成电路的成本及性能方面的问题越来越突出,基于TSV技术的三维集成已成为研究热点,并很有可能是未来集成电路发展的方向.在三维集成中,键合技术为芯片堆叠提供电学连接和机械支撑,从而实现两层或多层芯片间电路的垂直互连.介绍了几种晶圆级三维集成键合技术的特点及研究现状.     

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown(TDDB) characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy(SIMS) analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio N_(it)/N_(ot) are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo(kMC) method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.     

具有夹层的垂直U型栅极TFET的设计

通过使用工艺计算机辅助设计(TCAD)仿真技术提出了一种新型的带有夹层的垂直U型栅极隧穿场效应晶体管(TFET)结构.该器件是通过优化基于Ge的栅极金属核垂直纳米线TFET结构获得的.通过在沟道中增加重掺杂夹层,器件的平均亚阈值摆幅(SSavg)得到了改善;又通过改变器件的源极和漏极材料,器件的开关电流比(Ion/Ioff)得到了改善.对夹层的掺杂浓度和厚度以及沟道的高度也进行了优化.最终优化后的器件开态电流为220 μA/μm,关态电流为3.08×10-10μA/pm,SSavg为8.6 mV/dec,表现出了优越的性能.与初始器件相比,该器件的SSavg减小了 77％,Ion/Ioff增加了两个数量级以上.此外,提出了针对该器件的可行的制备工艺步骤.因此,认为该器件是在超低功耗应用中非常具有潜力的候选器件.     

关于超薄埋氧层及超薄SOI的MOSFET器件衬底掺杂的设计研究

The importance of substrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide(ES-UB-MOSFETs) is demonstrated by simulation.A new substrate/backgate doping engineering,lateral non-uniform dopant distributions(LNDD) is investigated in ES-UB-MOSFETs.The effects of LNDD on device performance,V t-roll-off,channel mobility and random dopant fluctuation(RDF) are studied and optimized.Fixing the long channel threshold voltage(V t) at 0.3 V,ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm,meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length,which is 43% smaller.The LNDD degradation is 10% of the carrier mobility both for n MOS and p MOS,but it is canceled out by a good short channel effect controlled by the LNDD.Fixing V t at 0.3 V,in long channel devices,due to more channel doping concentration for the LNDD technique,the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs,but in the short channel,the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer.A novel process flow to form LNDD is proposed and simulated.