LaTiO高k栅介质Ge MOS电容电特性及Ti含量优化

采用共反应溅射法将Ti添加到La_2O_3中,制备了LaTiO/Ge金属-氧化物-半导体电容,并就Ti含量对器件电特性的影响进行了仔细研究.由于Ti-基氧化物具有极高的介电常数,LaTiO栅介质能够获得高k值;然而由于界面/近界面缺陷随着Ti含量的升高而增加,添加Ti使界面质量恶化,进而使栅极漏电流增大、器件可靠性降低.因此,为了在器件电特性之间实现协调,对Ti含量进行优化显得尤为重要.就所研究的Ti/La_2O_3比率而言,18.4%的Ti/La_2O_3比率最合适.该比率导致器件呈现出高k值(22.7)、低D_(it)(5.5×10~(11)eV~(-1)·cm~(-2))、可接受的J_g(V_g=1V,J_g=7.1×10~(-3)A·cm~(-2))和良好的器件可靠性.     

Effect of interface-roughness scattering on mobility degradation in SiGe p-MOSFETs with a high-k dielectric/SiO2 gate stack＊

A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer （SiO2） thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer, as well as moderate permittivities of high-k dielectrics, is highly desired to improve carriers mobility while keeping alow equivalent oxide thickness. Simulated results agree reasonably with experimental data.     

A threshold voltage model MOSFETs considering for high-k gate-dielectric fringing-field effect

In this paper, a threshold voltage model for high-k gate-dielectric metal-oxide-semiconductor field-effect transistors （MOSFETs） is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-k gate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-k gate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.     

Fabrication and Characteristics of Nano-Floating Gate Memories with ZnO Nano-Crystals as Charge-Storage Layer

Nano-floating gate memory devices with ZnO nano-crystals as charge storage layers are fabricated,and the influence of post-deposition annealing temperature and thickness of the ZnO layer are investigated.Atomic force microscopy and scanning electron microscopy reveal the morphology of discrete ZnO nano-crystals.For capacitance-voltage measurements,it is found that the memory device with 1.5 nm ZnO and annealed at 700℃shows a larger memory window of 4.3 V(at±6 V)and better retention characteristics than memoriy devices with2.5 nm ZnO or annealed at other temperatures.These results indicate that the nano-floating gate memory with ZnO nano-crystals can obtain good trade-off memory properties.     

Improvements of Interfacial and Electrical Properties for Ge MOS Capacitor with LaTaON Gate Dielectric by Optimizing Ta Content

The interfacial and electrical properties of high-k LaTaON gate dielectric Ge metal-oxide-semiconductor(MOS)capacitors with different tantalum(Ta) contents are investigated. Experimental results show that the Ge MOS capacitors with a Ta content of ~30% exhibit the best interfacial and electrical properties, including low interfacestate density(7.6 × 10~(11) cm~(-2) eV~(-1)), small gate-leakage current(8.32 × 10~(-5) A/cm~2) and large equivalent permittivity(22.46). The x-ray photoelectron spectroscopy results confirm that the least GeO_x is formed at the Ge surface for the sample with a Ta content of ~30% due to the effective blocking role of Ta against O diffusion and the greatly improved hygroscopicity of LaON.     

高k栅介质GeOI金属氧化物半导体场效应管阈值电压和亚阈斜率模型及其器件结构设计

通过求解沟道与埋氧层的二维泊松方程,同时考虑垂直沟道与埋氧层方向的二阶效应,建立了高κ栅介质GeOI金属氧化物半导体场效应管(MOSFET)的阈值电压和亚阈斜率解析模型,研究了器件主要结构参数对器件阈值特性、亚阈特性、短沟道效应、漏极感应势垒降低效应及衬偏效应的影响,提出了优化器件性能的结构参数设计原则及取值范围,模拟结果与TCAD仿真结果符合较好,证实了模型的正确性与实用性。     

高$lt;i$gt;k$lt;/i$gt;栅介质小尺寸全耗尽绝缘体上锗p型金属氧化物半导体场效应晶体管漏源电流模型

通过求解沟道的二维泊松方程得到沟道表面势和沟道反型层电荷, 建立了高k栅介质小尺寸绝缘体上锗(GeOI) p型金属氧化物半导体场效应晶体管(PMOSFET)的漏源电流解析模型. 模型包括了速度饱和效应、迁移率调制效应和沟长调制效应, 同时考虑了栅氧化层和埋氧层与沟道界面处的界面陷阱电荷、氧化层固定电荷对漏源电流的影响. 在饱和区和非饱和区, 漏源电流模拟结果与实验数据符合得较好, 证实了模型的正确性和实用性. 利用建立的漏源电流模型模拟分析了器件主要结构和物理参数对跨导、漏导、截止频率和电压增益的影响, 对GeOI PMOSFET的设计具有一定的指导作用. 关键词： 绝缘体上锗p型金属氧化物半导体场效应晶体管 漏源电流模型 跨导 截止频率     

不同散射机理对 Al2O3/InxGa1-xAs nMOSFET 反型沟道电子迁移率的影响

通过考虑体散射、界面电荷的库仑散射以及 Al₂O₃/In_xGa_1-xAs 界面粗糙散射等主要散射机理, 建立了以 Al₂O₃为栅介质In_xGa_1-xAs n 沟金属-氧化物-半导体场效应晶体管 (nMOSFETs) 反型沟道电子迁移率模型, 模拟结果与实验数据有好的符合. 利用该模型分析表明, 在低至中等有效电场下, 电子迁移率主要受界面电荷库仑散射的影响; 而在强场下, 电子迁移率则取决于界面粗糙度散射. 降低界面态密度, 减小 Al₂O₃/In_xGa_1-xAs 界面粗糙度, 适当提高In含量并控制沟道掺杂在合适值是提高 InGaAs nMOSFETs 反型沟道电子迁移率的主要途径. 关键词： InGaAs MOSFET 反型沟道电子迁移率 散射机理     

P／I界面处理对a-Si：H柔性太阳能电池性能的影响

采用等离子体辅助化学汽相沉积(PECVD)技术制备本征非晶硅薄膜,对p/i界面进行处理.在此基础上,制备P型微晶硅(μc-Si:H)薄膜与柔性太阳能电池.对P型硅薄膜及太阳能电池的性能进行研究.结果表明:对p/i界面采用H等离子体处理,再引入一定厚度的成核层,可以成功得到高电导率的P型微晶硅窗口层,提高柔性太阳能电池的光伏特性.其中的成核层,不仅促进微晶相P层的生长,还可以起到界面缓冲层的作用.     

退火工艺对LaTiON和HfLaON存储层金属-氧化物-氮化物-氧化物-硅存储器特性的影响

采用反应溅射法, 分别制备以LaTiON, HfLaON为存储层的 金属-氧化物-氮化物-氧化物-硅 电容存储器, 研究了淀积后退火气氛(N₂, NH₃)对其存储性能的影响. 分析测试表明, 退火前LaTiON样品比HfLaON 样品具有更好的电荷保持特性, 但后者具有更大的存储窗口 (编程/擦除电压为+/-12 V时4.8 V); 对于退火样品, 由于NH₃的氮化作用, NH₃退火样品比N₂退火样品表现出更快的编程/擦除速度、更好的电荷保持特性和疲劳特性. 当编程/擦除电压为+/-12 V时, NH₃退火HfLaON样品的存储窗口为3.8 V, 且比NH₃退火LaTiON样品具有更好的电荷保持特性和疲劳特性.