The paper proposes a rational method to derive fairness measures for surfaces. It works in cases where isophotes, reflection lines, planar intersection curves, or other curves are used to judge the fairness of the surface. The surface fairness measure is derived by demanding that all the given curves should be fair with respect to an appropriate curve fairness measure. The method is applied to the field of ship hull design where the curves are plane intersections. The method is extended to the case where one considers, not the fairness of one curve, but the fairness of a one parameter family of curves. Six basic third order invariants by which the fairing measures can be expressed are defined. Furthermore, the geometry of a plane intersection curve is studied, and the variation of the total, the normal, and the geodesic curvature and the geodesic torsion is determined. 相似文献
Metal/insulator/semiconductor junctions are prepared on degeneratep-type InAs substrates with hole concentrations ranging from 2.3×1017 cm–3 to 2.7×1018 cm–3. The low work function of the top metal Yb, Al, or Au and charged interface states influence a two-dimensional (2D) electron inversion layer at the InAs surface. The insulator barrier that is formed by thermal oxidation is designed sufficiently thin, so that the bias voltage applied at the metal electrode mainly drops across the depletion layer separating the electron channel from the bulk. The current-voltage (I–V) characteristics exhibit strong negative differential conductance due to interband, tunneling from the 2D subband into the 3D valence band with peak-to-valley current ratios up to 3.1, 18, and 32 at 300 K, 77 K, and 4.2 K, respectively. In agreement with a theoretical model based on coherentelastic tunneling, the form of the I–V curves resembles those of double-barrier resonant tunnel devices rather than those of 3D Esaki diodes. The series resistance is obtained from the saturation of the differential conductance dI/dV at high forward bias and from the shift of structures in d2I/dV2 arising from phonon assisted tunneling.Dedicated to G. Lautz on the occasion of his 65th birthday 相似文献
We consider the following problem: given a set of points in the plane, each with a weight, and capacities of the four quadrants, assign each point to one of the quadrants such that the total weight of points assigned to a quadrant does not exceed its capacity, and the total distance is minimized.
This problem is most important in placement of VLSI circuits and is likely to have other applications. It is NP-hard, but the fractional relaxation always has an optimal solution which is “almost” integral. Hence for large instances, it suffices to solve the fractional relaxation. The main result of this paper is a linear-time algorithm for this relaxation. It is based on a structure theorem describing optimal solutions by so-called “American maps” and makes sophisticated use of binary search techniques and weighted median computations.
This algorithm is a main subroutine of a VLSI placement tool that is used for the design of many of the most complex chips. 相似文献