A buffer insertion and simultaneous sizing timing optimization algorithm

A path-based timing optimization algorithm for buffer insertion and simultaneous sizing is proposed. Firstly, candidate buffer insertion location and buffer size for each branch in a given routing path were obtained via localized timing optimization. Then, through evaluating each potential insertion against design objectives, potential optimal buffer insertion locations and sizes for the whole routing tree were determined. At last, by removing redundant buffer insertion operations which do not maximize S （ so ）, given timing requirements are finally fulfilled through minimum number of buffers.     

车身零件定位方案的多变量稳健设计

在新车型初始设计阶段仅有零件的A面数据或初步结构为已知的情况下，提出了一种在初始设计阶段零件装配的定位方案稳健设计方法，建立了基于刚性零件确定性定位和稳健设计理论的定位方案优化设计模型，使用遗传算法在可行定义域内求解最优定位点的位置，并提取了定位点偏差对整体装配效果的敏感度系数，实现了在优化公差的同时控制生产成本.同时，以某新车型前大灯的定位方案设计为例，验证了所提方法在初始设计阶段的有效性.     

时序分析中时序约束条件的确立和检验算法

针对同步多相时序电路在满足建立时间约束时却忽视保持时间约束的情况，提出了一个基于锁存器多相时序电路的建立时间约束和保持时间约束的检验算法。该算法考虑了时钟偏斜对建立时间和保持时间的影响。经具体时序电路验证，本文检验算法是可行的。     

驱动器等效电路模型中电阻及电容的计算

为了找到一种计算驱动器的戴维南等效电路模型中电阻和电容值的方法,在负载电容分别取最小和最大值时,从驱动器输出仿真曲线上选择2个不同的输出电压,根据其对应的门负载延迟解出输出电阻和电容。计算结果表明,当输出电压从终值电压的30％、40％和50％中选择任意2个参考电压时,算出的输出电阻和电容值绘制的驱动器输出曲线较逼近Spice仿真曲线。     

Uniform wire segmentation algorithm of distributed interconnects

A uniform wire segmentation algorithm for performance optimization of distributed RLC interconnects was proposed in this paper. The optimal wire length for identical segments and buffer size for buffer inser-tion are obtained through computation and derivation, based on a 2-pole approximatian model of distribut-ed RLC interconnect. For typical inductance value and long wires under 180nm technology, experiments show that the uniform wire segmentation technique proposed in the paper can reduce delay by about 27%～56%, while requires 34%～69% less total buffer usage and thus 29% to 58% less power consump-tion. It is suitable for long RLC interconnect performance optimization.     

一种新的RLC互连解析延时模型的建立

提出了用来评估深亚微米VLSI电路中RLC互连延时的一种新的解析延时模型．该模型的驱动器由输出电阻和电容组成，负载为容性负载．先对分布式均匀传输线的转换函数展开式进行二阶近似，然后根据不同的极点情况，计算出时域下的阶跃响应及相应的解析延时．该模型还被应用到具体的RLC互连树中评估源节点到漏节点的延时．实验结果表明，该模型比前人的延时模型精确，延时评估误差减少了10%；而由输出电阻和电容组成的驱动器能够很好地改善RLC互连树的延时分析．