Common-mode oscillation in capacitivecoupled differential Colpitts oscillators

A simple approach to the realisation of a differential Colpitts oscillator is to connect the grounded capacitor in the feedback network of two single-ended Colpitts oscillators together in series. As the output signals are expected to be differential, it is proved in this Letter that, this is not always the case. In certain circumstances, this topology exhibits a common-mode output signal, or even worse, a combination between differential-mode and common-mode waveforms. Design criteria for avoiding these undesirable oscillating behaviours are derived by considering the start-up characteristic of the oscillator.     

Simple topology for low-voltage and low-power RF quadrature oscillators

A design technique for implementing a low-voltage and low-power quadrature oscillator operating at radio frequencies is proposed. The oscillator utilises a cascade of four stages of capacitive-source amplifiers to generate balanced quadrature signals. The analysis provides a set of design equations that matches the simulation results.     

Regulated cascode-based vertical filter

An approach to realise a low-power, high-order, very-high-frequency current-mode filter is proposed. The filter utilises vertical connection of regulated-cascode (RGC) biquads to reduce current consumption. Simulation results of a fourth-order Chebyshev lowpass filter are demonstrated     

Bulk-source-coupled CMOS quadrature oscillators

A quadrature oscillator based on a coupling between the bulk and the source of MOS transistors is proposed. Since the resonator load is not directly involved in the coupling process, the oscillation frequency is very close to the resonant frequency, hence a good phase noise characteristic. The developed theory matches very well to the simulations.     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

High-precision CMOS current conveyor

A CMOS current conveyor suitable for high-precision analogue signal processing is presented. Local negative feedback is employed for minimising voltage variations at critical nodes, thus achieving very high accuracy in the transfer characteristics. Simulation results confirming the performance of the circuit are included