Fluid-fluid phase separation in colloid-polymer mixtures studied with small angle light scattering and light microscopy

Mixtures of colloidal silica spheres and polydimethylsiloxane in cyclohexane with a colloid-polymer size ratio of about one were found to phase separate into two fluid phases, one which is colloid-rich and one which is colloid-poor. In this work the phase separation kinetics of this fluid-fluid phase separation is studied for different compositions of the colloid-polymer mixtures, and at several degrees of supersaturation, with small angle light scattering and with light microscopy. The small angle light scattering curve exhibits a peak that grows in intensity and that shifts to smaller wave vector with time. The characteristic length scale that is obtained from the scattering peak is of the order of a few μm, in agreement with observations by light microscopy. The domain size increases with time as , which might be an indication of coarsening by diffusion and coalescence, like in the case of binary liquid mixtures and polymer blends. For sufficiently low degrees of supersaturation the angular scattering intensity curves satisfy dynamical scaling behavior.     

Smoothing Streams in an In-Home Digital Network: Optimization of Bus and Buffer Usage

In an in-home digital network it may be expected that several data streams (audio, video) run simultaneously over a shared communication device, e.g., a bus. The burstiness of a data stream can be reduced by buffering data at the sending and receiving side, thereby allowing a lower bus share allocation for the stream. In this paper we present an algorithm that determines how much of the bus capacity and buffer space should be allocated to each stream, in order to have a feasible transmission schedule for each stream. Furthermore, the algorithm determines a transmission schedule for each stream, indicating how much data is transmitted over time. We show how this multiple-stream problem can be solved by repeatedly solving single-stream problems. We present efficient algorithms to solve these single-stream problems. Furthermore, we present some experimental results. This revised version was published online in September 2006 with corrections to the Cover Date.     

Architectural strategies for high-throughput applications

In this article an architecture is presented which allows efficient ASIC implementations of high throughput applications. Examples of these applications can be found in real time video applications such as EDTV, IDTV and HDTV. A key issue in the architecture is to provide a balance between memory resources and processing resources. Special attention is paid to the communication between these two types of resources. Architectural techniques are proposed to solve bottlenecks in the memory bandwidth and conflicts between memory accesses. Architectures for address generation in combination with location assignment are presented. The flexibility of the architectural model allows an efficient hardware realization on an ASIC exploiting the inherent parallelism of a particular application. This is illustrated in the article using a complex video algorithm for Progressive Scan Conversion. The proposed architecture is used as a target architecture which drives the high-level synthesis approach of the PHIDEO compiler.     

Mpeg2 Video Encoding in Consumer Electronics

Only very recently, single-chip MPEG2 video encoders are being reported. They are a result of additional interest in encoding in consumer products, apart from broadcast encoding, where a video encoder contains several expensive chips. Only single-chip solutions are cost-effective enough to enable digital recording for the consumer. The professional broadcast encoders are expensive because they use the full MPEG toolkit to guarantee good image quality, at the lowest possible bit-rate. Some MPEG tools are costly in hardware and these are therefore not feasible in single-chip solutions. This results in higher bit-rates, that can be accepted because of the available channel and storage capacity of the latest consumer storage media, harddisk, digital tape (D-VHS) and Digital Versatile Disk (DVD). A consumer product is I.McIC, a single-chip MPEG2 video encoder. It operates in ML@SP mode which can be decoded by all MPEG2 decoders. The IC is highly-integrated, as it contains motion-estimation and compensation, adaptive temporal noise filtering and buffer/bit-rate control. The high-throughput functions of the MPEG algorithm are mapped onto pipelined dedicated hardware, whereas the remaining functions are processed by an application-specific instruction-set processor. Software for this processor can be downloaded, in order to suit the IC for different applications and operating conditions. The IC consists of several communicating processors which were designed using high-level synthesis tools, PHIDEO and DSP Station.     

PHIDEO: High-level synthesis for high throughput applications

This paper describes a new approach to high-level synthesis for high throughput applications. Such applications are typically found in real-time video systems such as HDTV. The method is capable of dealing with hierarchical flow graphs containing loops with manifest boundaries and linear index expressions. The algorithm is based on the model of periodic operations which allows optimizations across loop boundaries. Processing units and storage units are minimized simultaneously. The algorithm is implemented in thePHIDEO system. The major parts of this system are the processing unit synthesis, the scheduler and the memory synthesis including address generation.