Triangularly weighted zero-crossing detector providingΣΔ frequency-to-digital conversion

It is shown that for delta-sigma (ΣΔ) frequency-to-digital conversion (FDC) there is no need for a ΣΔ modulator, since a limited FM signal itself may be considered as an asynchronous ΣΔ bit-stream. By feeding the limited FM signal directly to a sinc² ΣΔ decimator, a triangularly weighted zero-crossing counter FDC is introduced, providing ΣΔ noise shaping. The results measured confirm the theory     

Equalization for discrete multitone transceivers to maximize bitrate

In a discrete multitone receiver, a time-domain equalizer (TEQ) reduces the intersymbol interference (ISI) by shortening the effective duration of the channel impulse response. Current TEQ design methods such as the minimum mean-squared error (MMSE), maximum shortening SNR (MSSNR), and maximum geometric SNR (MGSNR) do not directly maximize bit rate. We develop two TEQ design methods to maximize the bit rate. First, we partition an equalized multicarrier channel into its equivalent signal, noise, and ISI paths to develop a new subchannel SNR definition. Then, we derive a nonlinear function of TEQ taps that measures the bit rate, which the proposed maximum bit rate (MBR) method optimizes. We also propose a minimum-ISI method that generalizes the MSSNR method by weighting the ISI in the frequency domain to obtain higher performance. The minimum-ISI method is amenable to real-time implementation on a fixed-point digital signal processor. Based on simulations using eight different carrier-serving-area loop channels, (1) the proposed methods yield higher bit rates than MMSE, MGSNR, and MSSNR methods; (2) the proposed methods give three-tap TEQs with higher bit rates than 17-tap MMSE, MGSNR, and MSSNR TEQs; (3) the proposed MBR method achieves the channel capacity (as computed by the matched filter bound using the proposed subchannel SNR model) with a five-tap TEQ; and (4) the proposed minimum-ISI method achieves the bit rate of the optimal MBR method     

On-line adaptive digital correction of dual-quantisation delta-sigma modulators

The authors describe the digital adaptive correction of nonidealities in dual-quantisation delta-sigma modulators. The sources and effects of nonidealities in a delta-sigma loop are discussed, and a simple on-line correction scheme is presented. The theoretical signal-to-noise ratio (SNR) improvement is calculated and simulation results are given which illustrate the effectiveness of the technique.<>     

Combined Linear and $Delta$-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters

A combined linear and delta-modulated (DeltaM) switch-mode PA supply modulator for polar transmitters in wireless handsets is designed in a 0.25 mum CMOS process. The modulator employs a DeltaM switch-mode DC-DC buck converter to enhance the efficiency of a linear regulator at backed-off supply voltages and powers. The delta-modulator's noise-shaping characteristic, linear regulator's power supply rejection, digital pre-emphasis of the input envelope, and a closed-loop amplitude path from the PA output are simultaneously used to achieve state-of-the-art modulator performance. The presented supply modulator follows the input signal's envelope with 20 dB output dynamic range, maximum efficiency of 75.5% at an output power of 30.8 dBm, and 75 dB SFDR for envelope signals up to 4 MHz occupied RF bandwidth. For a 1625 kb/s 8 PSK RF input signal at 900 MHz, polar modulation of a commercial low-power GSM-900 PA provides 10 dB ACPR improvement.     

Noise considerations for mixed‐signal RF IC transceivers

This paper discusses design tradeoffs for mixedsignal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multipath fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit nonlinearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design tradeoffs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixedsignal noise coupling and to model substrate noise effects are presented.     

A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With −75 dBc Single-Tone Sensitivity at 100 kHz Offset

An on-chip clock phase-noise measurement circuit is presented. Unlike previously reported monolithic measurement techniques that measure jitter in the time domain, the proposed module measures the phase-noise spectrum. The proposed circuit is fully integrated and does not require a spectrally clean reference clock or any external calibration. The module can be integrated as part of a built-in self-test (BIST) scheme for PLL clock synthesizers. The proposed circuit uses a low-noise voltage-controlled delay-line (VCDL) and mixer-based frequency discriminator to extract the phase-noise fluctuations at baseband. A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point. The proposed circuit is fabricated using a 0.25 mum digital CMOS process and operates up to a 2 GHz carrier frequency. It achieves a single-tone measurement sensitivity of -75 dBc and an equivalent phase-noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.     

Adaptive selfcalibrating delta-sigma modulators

The concept of an adaptive Delta Sigma A/D convertor is introduced. A selfcalibrating adaptive implementation is described. The new scheme appears to be very effective for improving the resolution and the signal-to-noise ratio of delta-sigma modulators which rely on error cancellation to achieve a high signal-to-noise ratio.<>     

Analog logic techniques steer around the noise

CMOS folded source-coupled logic (FSCL) and current-steering logic (CSL), developed to complement conventional CMOS static logic in high-precision mixed-signal applications, are examined. The key feature of FSCL and CSL is the reduction in power-supply noise-current spikes by two orders of magnitude or more compared to conventional CMOS logic. Hence, FSCL and CSL are attractive for the high-speed logic sections of CMOS mixed-mode integrated circuits, while conventional logic is appropriate for the low-speed digital subsections     

The volatile constituents analysis of Eremostachys macrophylla Montbr. & Auch. from Iran

The volatile constituents of the aerial parts of Eremostachys macrophylla growing in the wild in Iran have been examined by GC-FID and GC-MS. Altogether, 16 compounds were identified, constituting approximately 96.4% of the oil. The oil of E. macrophylla consisted mainly of germacrene-D (47.1%), germacrene-B (17.8%), gamma-elemene (9.1%), myrcene (6.7%), beta-elemene (2.7%), and beta-phellandrene (2.6%).