Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity

To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown.     

Low dose measurement with thick gate oxide MOSFETs

The low dose limit and the accuracy of high sensitivity MOS ionizing radiation dosimeters fabricated at LAAS-CNRS are investigated.     

MOSFET with a boron-loaded gate as a low-energy neutron dosimeter

A MOSFET-based low-energy neutron dosimeter has been fabricated using a ¹⁰B loaded gate electrode as (n,α) converter. The response to thermal neutrons has been studied.     

MOS ionizing radiation dosimeters: from low to high dose measurement

Metal-oxide-silicon dosimeters with a very thick gate oxide in a stack-connected configuration are studied with respect to their capability to measure a low dose. It is shown that if the temperature is controlled to ±5°C during reading a dose as low as 10⁻⁴ Gy can be measured with 10% accuracy.     

Thickness measurement of thin oxide layers in MOS capacitors

The validity of the SiO/sub 2/ layer thickness determined from capacitance-voltage measurements in MOS devices is demonstrated by comparison with results obtained by X-ray photoelectron spectroscopy, high-resolution transmission electron microscopy and spectroscopic ellipsometry published elsewhere in the literature.<>     

Radiation dose measurment using MOSFETs

The MOS transistor as a radiation dose detector has been presented. MOS transistors present advantages such as low cost, small volume and weight, robustness, accuracy, large measurable dose range, and sensitivity to low-energy radiation (10 keV). They are useful in real-time measurements or post-irradiation read-out, while they retain information after reading. The sensitivity of unbiased MOSFETs has been improved, and further improvement is possible by increasing the oxide thickness via dual dielectrics or by using ion-implanted oxides and stacked MOSFET configurations. The stacked-transistor configuration is a very promising solution to reach the mRad range (personnel dosimetry). MOSFETs are already used in various application fields with increasing interest for use in specific cases of in-vivo dosimetry     

Application of a floating well concept to a latch-up-free,low-cost, smart power high-side switch technology

An original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology is presented. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up     

Reduction of the parasitic charge generation during silicon nitride deposition in a LOCOS isolation without field implant

MOS integrated circuits use the Local oxidation of silicon to isolate laterally adjacent devices (LOCOS isolation). The insulation structure is typically formed by a semiconductor region doped by ion implantation (field implant) and covered by a thick thermal oxide (field oxide). Other insulators (plasma enhanced chemical vapor deposited (PECVD) silicon oxides and LPCVD silicon nitride) and metal interconnection are subsequently deposited on the field oxide. The ion implant together with the thick insulator ensure a high threshold voltage value of the parasitic MOS transistor formed by source and drain of the adjacent active devices and by the insulator/interconnection gate.However, economical purpose leads to the extension of the application field of lower cost technology, addressing the problem of LOCOS isolation without any field implant. As already shown in a previous work [Fay JL, Beluch J, Allirand L, Brosset D, Despax B, Bafleur M, Sarrabayrose G. Jpn J Appl Phys 38(9A):5012–7] for inter-layer dielectric applications, our PECVD oxides suffer from excessive concentration of fixed positive charges brought about by the silicon nitride deposition, and causing the N-channel field threshold voltage to decrease.Characterization reveals that these charges are generated by diffusion of species coming from the gas phase during the silicon nitride process. These generated charges can be reduced either by increasing the O₂/tetra-ethyl orthosilicate ratio or by doping the oxide with boron and phosphorus. To avoid diffusion and generation of charges, we minimized the thermal budget using a PECVD silicon nitride. With this process, we have achieved a high threshold voltage and an acceptably low leakage current of the NMOS parasitic transistor.