A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA

A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm/sup 2/ including the bonding pads.     

WCDMA multicarrier receiver for base-station applications

The multicarrier receiver IC described in this paper receives four adjacent WCDMA channels simultaneously in order to reduce the component count of a base-station. The receiver uses low-IF architecture and it is fabricated with a 0.25-/spl mu/m SiGe BiCMOS process to meet the high-performance requirements set by the base-station application. The receiver includes a dual-input low-noise amplifier (LNA), quadrature mixers, a local-oscillator (LO) divider, IIP2 calibration circuits, 10-MHz low-pass filters, and ADC buffers. The receiver noise figures, measured over the downconverted WCDMA channels centered at 2.5-MHz and 7.5-MHz intermediate frequencies, are 3.0 dB and 2.6 dB, respectively. The receiver achieves 47-dB voltage gain and -12-dBm out-of-band IIP3 and consumes 535mW from a 2.5-V supply.     

Calibration techniques of active BiCMOS mixers

This paper describes calibration techniques for downconversion mixers used in integrated direct-conversion receivers. A method of achieving a high even-order intermodulation rejection is presented. Using the method presented, the receiver second-order input intercept point (IIP2) can always be improved by more than 20 dB. The minimum achieved receiver IIP2 after calibration is +38 dBm. A technique to enhance the I/Q-amplitude balance between the quadrature channels is also introduced. A single-balanced adjustable mixer is implemented as a part of a prototype direct-conversion receiver. The receiver chip consists of a low-noise amplifier, mixers and calibration circuitry, a divide-by-two circuit, local oscillator (LO) buffers for LO generation, and active baseband filters. The chip is fabricated using a 0.35-μm SiGe BiCMOS process and is characterized at 900 MHz     

A dual-band RF front-end for WCDMA and GSM applications

An RF front-end for dual-band dual-mode operation is presented. The front-end consumes 22.5 mW from a 1.8-V supply and is designed to be used in a direct-conversion WCDMA and GSM receiver. The front-end has been fabricated in a 0.35-μm BiCMOS process and, in both modes, can use the same devices in the signal path except the LNA input transistors. The front-end has a 27-dB gain control range, which is divided between the LNA and quadrature mixers. The measured double-sideband noise figure and voltage gain are 2.3 dB, 39.5 dB, for the GSM and 4.3 dB, 33 dB for the WCDMA, respectively. The linearity parameters IIP3 and IIP2 are -19 dBm, +35 dBm for the GSM and -14.5 dBm and +34 dBm for the WCDMA, respectively     

A 22-mA 3.0-dB NF direct conversion receiver for 3G WCDMA

A 2-GHz single-chip direct conversion receiver achieves a 3.0-dB double-sideband noise figure, -14-dBm IIP3 and +17-dBm IIP2 with 60-mW power consumption from a 2.7-V supply. The receiver is targeted for the third generation UTRA/FDD WCDMA system. The low power consumption has been achieved with a proper partitioning and by avoiding buffering between blocks. In the differential RF front end, current boosted quadrature mixers follow the variable-gain low-noise amplifier. At the baseband, on-chip ac-coupled highpass filters are utilized to implement amplification with variable gain having small transients related to gain steps. The outputs of the analog channel selection filters are sampled directly by the two single-amplifier 6-bit pipeline A/D converters. The spurious tones due to the feedthrough of clock harmonics to the RF input increase the noise figure less than 0.1 dB. The receiver has been fabricated with a 0.35-μm 45-GHz f_T SiGe BiCMOS process     

Multitone Fast Frequency-Hopping Synthesizer for UWB Radio

A fast frequency-hopping six-band local oscillator signal generator is described in this paper. Targeted for a Wi-Media ultra-wideband radio transceiver, it offers operation in mandatory band group 1 and in extensional band group 3. The circuit entity consists of three parallel phase-locked loops (PLLs), each including two voltage-controlled oscillators, one per band group, and a signal multiplexer for fast frequency selection. A broadband poly-phase RC filter is used for in-phase/quadrature generation. Furthermore, the synthesizer generates the clock signal for analog-to-digital converters by mixing the signals from the first and third PLL. The circuit was fabricated in a 0.13- mum CMOS process and it consumes 32 mA from a 1.2-V supply. It achieves 2-ns frequency settling time with a 3-MHz hopping rate.     

A 2-GHz wide-band direct conversion receiver for WCDMA applications

A 2-GHz direct conversion receiver for third-generation mobile communications using wide-band code division multiple access achieves -114-dBm sensitivity for 128-kb/s data at 4.096-Mcps spreading rate. The receiver is distributed on four dies. The active RC channel selection filter can be programmed to three different bandwidths from 5 to 20-MHz radio-frequency (RF) spacing; and the gain control is merged with filtering. RF and baseband chips use a 25-GHz, 0.3-μm BiCMOS technology while the two analog-to-digital converters are implemented with a 0.5-μm CMOS. The double-sideband noise figure is 5.1 dB at the 94-dB maximum voltage gain, and the IIP3 and ITP2 are -9.5 and +38 dBm, respectively, The receiver draws 128 mA from a 2.7-V supply     

2.4-GHz receiver for sensor applications

This paper describes a receiver designed to meet the stringent power consumption requirements for sensor radio, which operates at 2.4-GHz ISM band with Bluetooth. To enable the reusability of the Bluetooth system, only slight changes are made in the radio parameters. The symbol rate is decreased and the increased modulation index removes the energy maximum from the channel center, which enables a low-complexity direct-conversion receiver solution. To meet the speed and power requirements, this receiver is fabricated in a 0.13-/spl mu/m CMOS process. The 3.4-mW direct-conversion demonstrator receiver includes a low-noise amplifier, which is merged with quadrature mixers, local oscillator buffers, and one analog baseband channel with a 1-bit limiter for analog-to-digital conversion. The receiver consumes 2.75 mA from a 1.2-V supply. The receiver achieves 47-dB voltage gain, 28-dB NF, -21-dBm IIP3, and +18-dBm IIP2.