3D‐morphology reconstruction of nanoscale phase‐separation in polymer memory blends

In many organic electronic devices functionality is achieved by blending two or more materials, typically polymers or molecules, with distinctly different optical or electrical properties in a single film. The local scale morphology of such blends is vital for the device performance. Here, a simple approach to study the full 3D morphology of phase‐separated blends, taking advantage of the possibility to selectively dissolve the different components is introduced. This method is applied in combination with AFM to investigate a blend of a semiconducting and ferroelectric polymer typically used as active layer in organic ferroelectric resistive switches. It is found that the blend consists of a ferroelectric matrix with three types of embedded semiconductor domains and a thin wetting layer at the bottom electrode. Statistical analysis of the obtained images excludes the presence of a fourth type of domains. The criteria for the applicability of the presented technique are discussed. © 2015 Wiley Periodicals, Inc. J. Polym. Sci., Part B: Polym. Phys. 2015 , 53, 1231–1237     

Light and heat control over secondary structure and amyloid-like fiber formation in an overcrowded-alkene-modified Trp zipper

The external photocontrol over peptide folding, by the incorporation of molecular photoswitches into their structure, provides a powerful tool to study biological processes. However, it is limited so far to switches that exhibit only a rather limited geometrical change upon photoisomerization and that show thermal instability of the photoisomer. Here we describe the use of an overcrowded alkene photoswitch to control a model β-hairpin peptide. This photoresponsive unit undergoes a large conformational change and has two thermally stable isomers which has major influence on the secondary structure and the aggregation of the peptide, permitting the phototriggered formation of amyloid-like fibrils.     

Sigma-delta modulators operating at a limit cycle

A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital-analog converter waveform asymmetry and a higher tolerance to clock imperfections. The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs.     

Training and optimization of an artificial neural network controlling a hybrid power filter

A hybrid power compensator (HPC) consisting of a static VAr compensator and a dynamic compensator needs to be optimally controlled during the compensation of nonlinear loads. The HPC must be controlled to meet minimum requirements in terms of power factor and harmonic distortion, while at the same time minimizing its total cost. An artificial neural network (ANN) is used to control the HPC amidst a very dynamic power system environment. The performance of a reference ANN is evaluated while controlling an HPC connected to a typical nonlinear industrial load. The training and performance of the ANN is then optimized in terms of training set size, training set packing and ANN topology and the performance compared to the reference ANN. This paper highlights the importance of optimising the mentioned ANN parameters to achieve optimum ANN training and modeling accuracy. The results obtained reveals that the application of an ANN in controlling an HPC is feasible given that the ANN parameters are chosen appropriately.     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

Synchronous Full-Scan for Asynchronous Handshake Circuits

Handshake circuits form a special class of asynchronous circuits that has enabled the industrial exploitation of the asynchronous potential such as low power, low electromagnetic emission, and increased cryptographic security. In this paper we present a test solution for handshake circuits that brings synchronous test-quality to asynchronous circuits. We add a synchronous mode of operation to handshake circuits that allows full controllability and observability during test. This technique is demonstrated on some industrial examples and gives over 99% stuck-at fault coverage, using test-pattern generators developed for synchronous circuits. The paper describes how such a full-scan mode can be achieved, including an approach to minimize the number of dummy latches in case latches are used in the data path of the handshake circuit.