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1.
Conventional solid-state power amplifier (SSPA) design approach isolates radio frequency (RF) design from communication theory. In this paper, a unified SSPA design approach is proposed, which optimizes SSPA parameters (bias voltage and input RF signal power) to minimize total DC power consumption while satisfying received SNR constraint specified by the link budget. The effect of SSPA nonlinearity is quantified by the error vector magnitude measured at its output and the corresponding received SNR degradation is analyzed. Using the quantitative metrics for received SNR, it is possible to evaluate highly nonlinear SSPA classes such as Class-B or deep-Class AB, which are normally not considered in conventional SSPA design approach to be used in satellite communication applications.  相似文献   
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This paper reports three current mode second order filters, each of which realizes a specific function without any external passive elements. These filters realize low-pass notch (LPN), high-pass notch (HPN) and all-pass (AP) functions. Two OPAMPs, a double output OTA and a single output OTA are employed for each circuit. The filter structures can be easily cascaded since they have high output impedances. This property is especially useful for achieving high-order filters using these LPN and HPN filters as building blocks. The presented theory is verified with macro models in SPICE simulations and, using the SPICE parameters of the layout technology, post layout simulations are carried out, with parasitics extracted from the layouts of the filter chips.  相似文献   
4.
In this paper, a new rational approximation based on a rational interpolation and collocation method is proposed for the solutions of generalized pantograph equations. A comprehensive error analysis is provided. The first part of the error analysis gives an upper bound for the absolute error. The second part is based on residual error procedure that estimates the absolute error. Some numerical examples are given to illustrate the method. The theoretical results support the numerical results. Copyright © 2015 John Wiley & Sons, Ltd.  相似文献   
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The effects of the stress on shape memory properties of Cu-12.7Al-5Ni-2Mn shape memory alloy have been investigated. Applied stress increases transformation temperatures and the relationship between T0, temperature at which Gibbs free energy of austenite equals that of martensite, and plastic deformation is linear.  相似文献   
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In this brief, we first introduce a process-variation-aware test-point generation method. With this method, faults are not obscured by process variations and we are able to generate new test points by measuring a very limited number of current values on-chip and estimating values of the remaining currents. We furthermore introduce a multiple-fault diagnosis procedure where we use the process-variation aware test-point generation method. The proposed methods can also be used for structural test. For the application, we have used a thermometer coded current steering digital to analog converter, as they are widely used due to their suitability for high speed applications and the symmetric design is suitable for the application of our method. We introduce a design-for-test hardware for the diagnosis cost reduction, while implementing our methods. Experimental results show that parametric errors as small as 20% can be diagnosed with up to 97.8% accuracy  相似文献   
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Reaction of the oxo-molybdenum(V) compound, [MoTp*(O)Cl2], [Tp*=hydrotris(3,5-dimethylpyrazol-1-yl)borate] with p-methoxy and p-nitroaniline in the presence of Et3N under N2, afforded the oxo-bridged oxo(arylimido) molybdenum(V) complexes, [MoTp*(O)Cl](-O)[MoTp*(Cl)(NC6H4R)] (1, R=OMe; 2, R=NO2). The new compounds were characterized by elemental analysis, i.r., mass, and 1H-n.m.r. spectra. The single crystal X-ray crystallographic determination of [MoTp*(O)Cl](-O)[MoTp*(Cl)(NC6H4OMe)] was carried out to confirm that there is a Mo—O—Mo bridge and a near linear arylimido group in the structure.  相似文献   
8.
In this study, structural and optoelectronic properties and photodedection characteristics of diodes constructed from p-zinc telluride (ZnTe) thin film/n-silicon (Si) nanowire heterojunctions are reported. Dense arrays of vertically aligned Si nanowires were successfully synthesized on (1 1 0)-oriented n-type single crystalline Si wafer using simple and inexpensive metal-assisted etching (MAE) process. Following the nanowire synthesis, p-type ZnTe thin films were deposited onto vertically oriented Si nanowires via radio frequency magnetron sputtering to form three-dimensional heterojunctions. A comparative study of the structural results obtained from X-ray diffraction and Raman spectroscopy measurements showed the improved crystallinity of the ZnTe thin films deposited onto the Si nanowire arrays. The fabricated nanowire-based heterojunction devices exhibited remarkable diode characteristics and enhanced optoelectronic properties and photosensitivity in comparison to the planar reference. The electrical measurements revealed that the diodes with nanowires had a well-defined rectifying behaviour with a rectification ratio of 104 at ±2 V and a relatively small ideality factor of n = 1.8 with lower reverse leakage current and series resistance at room temperature in dark condition. Moreover, an open-circuit voltage of 100 mV was also observed under illumination. Based on spectral photoresponsivity measurements, the nanowire-based device exhibited a distinct responsivity and high detectivity in visible and near-infrared (NIR) wavelength regions. The device characteristics observed here offer that the fabricated ZnTe thin film/Si nanowire-based p–n heterojunction structures will find important applications in future and will be a promising candidate for high-performance and low-cost optoelectronic device applications, NIR photodedectors in particular.  相似文献   
9.
Chemical-mechanical polishing (CMP), active and via fills have become indispensable aspects of semiconductor manufacturing. CMP fills are used to reduce metal thickness variations due to chemical-mechanical polishing. Via fills are used to improve neighboring via printability and reliability of low-k and ultra low-k dielectrics. Active region fills are used for STI CMP uniformity and stress optimization. Although modern parasitic extraction tools accurately handle grounded fills and regular interconnects, such tools use only rough approximations to assess the capacitance impact of floating fills, such as assuming that floating fills are grounded or that each fill is merged with neighboring ones. To reduce such inaccuracies, we provide a design of experiments (DOE) which complements what is possible with existing extraction tools. Through the proposed DOE set, a design or mask house can generate normalized fill tables to correct for the inaccuracies of existing extraction tools when floating fills are present. Golden interconnect capacitance values can be updated using these normalized fill tables. Our proposed DOE enables extensive analyses of fill impacts on coupling capacitances. We show through 3-D field solver simulations that the assumptions used in extractors result in significant inaccuracies. We present analyses of fill impacts for an example technology and also provide analyses using the normalized fill tables to be used in the extraction flow for three different standard fill algorithms. We also extend our analyses and methodology to via fills and active region fills, which have more recently been introduced into semiconductor design-manufacturing methodologies and for which sufficient understanding is still lacking.  相似文献   
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