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1.
In this article, necessary optimality conditions for mathematical programming problems under generalized equation constraints problems are studied in Asplund spaces. We consider a very general version of the problem and derive necessary optimality conditions under various hypothesis on the problem data and sacrificing the differentiability assumption.  相似文献   
2.
The demand of low power high density integrated circuits is increasing in modern battery operated portable systems. Sub-threshold region of MOS transistors is the most desirable region for energy efficient circuit design. The operating ultra-low power supply voltage is the key design constraint with accurate output performance in sub-threshold region. Degrading of the performance metrics in Static random access memory (SRAM) cell with process variation effects are of major concern in sub-threshold region. In this paper, a bootstrapped driver circuit and a bootstrapped driver dynamic body biasing technique is proposed to assist write operation which improves the write-ability of sub-threshold 8T-SRAM cell under process variations. The bootstrapped driver circuit minimizes the write delay of SRAM cell. The bootstrapped driver dynamic body bias increases the output voltage levels by boosting factor therefore increasing in switching threshold voltage of MOS devices during hold and read operation of SRAM latch. The increment in threshold voltage improves the static noise margin and minimizing the process variation effects. Monte-Carlo simulation results with 3 \(\sigma \) Gaussian distributions show the improvements in write delay by 11.25 %, read SNM by 12.20 % and write SNM by 12.57 % in 8T-SRAM cell under process variations at 32 nm bulk CMOS process technology node.  相似文献   
3.
We have presented a comparative account of the high frequency prospective as well as noise behaviors of wide-bandgap 4H-SiC and 6H-SiC based on different structures of IMPATT diodes at sub-millimeter-wave frequencies up to 2.18 THz. The computer simulation study establishes the feasibility of the SiC based IMPATT diode as a high power density terahertz source. The most significant feature lies in the noise behavior of the SiC IMPATT diodes. It is noticed that the 6H-SiC DDR diode shows the least noise measure of 26.1 dB as compared to that of other structures. Further, it is noticed that the noise measure of the SiC IMPATT diode is less at a higher operating frequency compared to that at a lower operating frequency.  相似文献   
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5.
A competent and highly discriminating one-pot synthesis of highly diversified novel functionalized indenoquinoxalone grafted spiropyrrolidine linked chromene-3-carbonitrile conjugates accumulating three pharmocophoric cores, heterocyclic indenoquinoxalone, pyrrolidines and chromene-3-carbonitrile in a single molecular framework by means of 1,3-dipolar cycloaddition reaction between indenoquinoxalone, proline/benzyl amine and chromene-3-carbonitrile in ethanol under classical and microwave conditions is described. The three component 1,3-dipolar cycloaddition reaction proceeds via in situ generation of azomethine ylides by the decarboxylative condensation of indenoquinoxalone with proline/benzyl amine and their selectivity towards the endo cyclic double bonds of dipolarophile (chromene-3-carbonitrile) leading to the formation of highly functionalised regio- and diastereoselective molecular hybrids. This methodology exemplifies the green chemistry protocol such as mild reaction conditions, high yields, one-pot procedure and operational simplicity.  相似文献   
6.
Ionization rate coefficients and saturation drift velocities for electrons and holes are the vital material parameters in determining the performance of an IMPATT diode. We have performed a sensitivity analysis of the millimeter wave characteristics of 4H-SiC and 6H-SiC IMPATT diodes with reference to the above mentioned material data and an operating frequency of 220 GHz. The effect of a small variation in the ionization rate and drift velocity on the device characteristics like break down voltage, efficiency, noise measure and power output has been presented here.  相似文献   
7.
We have presented an analysis of the gate leakage current of the IP3 static random access memory (SRAM) cell structure when the cell is in idle mode (performs no data read/write operations) and active mode (performs data read/write operations), along with the requirements for the overall standby leakage power, active write and read powers. A comparison has been drawn with existing SRAM cell structures, the conventional 6T, PP, P4 and P3 cells. At the supply voltage, VDD = 0.8 V, a reduction of 98%, 99%, 92% and 94% is observed in the gate leakage current in comparison with the 6T, PP, P4 and P3 SRAM cells, respectively, while at VDD = 0.7 V, it is 97%, 98%, 87% and 84%. A significant reduction is also observed in the overall standby leakage power by 56%, the active write power by 44% and the active read power by 99%, compared with the conventional 6T SRAM cell at VDD = 0.8 V, with no loss in cell stability and performance with a small area penalty. The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor (CMOS) technology, tox = 2.4 nm, Vthn = 0.22 V, Vthp = 0.224 V, VDD = 0.7 V and 0.8 V, at T = 300 K.  相似文献   
8.
Device scaling is an important part of the very large scale integration(VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate(LPTG) approach and tested it on complementary metal oxide semiconductor(CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model(BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.  相似文献   
9.
An expedient one-pot sequential three-component synthesis of a series of diverse spiroindenoquinoxaline pyrrolidine fused nitrochromene derivatives following 1,3-dipolar cycloaddition of azomethine ylides generated in situ by the condensation of indenoquinoxalone and α-amino acids (L-proline and L-phenyl alanine) with 3-nitrochromenes as dipolarophile under classical as well as microwave irradiation is described. The protocol provides a mild reaction condition, high yield of the products, high regioselectivity, and operational simplicity to assemble complex structural entity in a single operation with good to excellent yield. The regio and stereochemical outcome of the cycloaddition reaction is ascertained by spectroscopic and single crystal X-ray analysis.  相似文献   
10.
Wireless Networks - Solutions for energy hole problem in wireless sensor networks (WSNs) have been excessively explored using mobile sink (MS). Although, MS provides a considerable amount of energy...  相似文献   
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