Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip

The second in the Niagara series of processors (Niagara2) from Sun Microsystems is based on the power-efficient chip multi-threading (CMT) architecture optimized for Space, Watts (Power), and Performance (SWaP) [SWap Rating = Performance/(Space _* Power) ]. It doubles the throughput performance and performance/watt, and provides >10times improvement in floating point throughput performance as compared to UltraSPARC T1 (Niagara1). There are two 10 Gb Ethernet ports on chip. Niagara2 has eight SPARC cores, each supporting concurrent execution of eight threads for 64 threads total. Each SPARC core has a floating point and graphics unit and an advanced cryptographic unit which provides high enough bandwidth to run the two 10 Gb Ethernet ports encrypted at wire speeds. There is a 4 MB Level2 cache on chip. Each of the four on-chip memory controllers controls two FBDIMM channels. Niagara2 has 503 million transistors on a 342 mm² die packaged in a flip-chip glass ceramic package with 1831 pins. The chip is built in Texas Instruments' 65 nm 11LM triple-Vt CMOS process. It operates at 1.4 GHz at 1.1 V and consumes 84 W.     

Importance sampling for estimation of false alarm probability

The purpose of this paper is to describe a technique of importance sampling for Monte Carlo simulation of Radar signal detectors under the ‘No Signal’ condition. The input to the detector is ‘restricted’ to a range that is more likely to cause a ‘false alarm’, thereby increasing the number of false alarms in a given sample. A model based on the theory of the Gauss-Markov process is developed so as to allow consideration of the case when the successive noise (clutter) samples are correlated. The technique enables estimation of very low false alarm probabilities with a relatively moderate sample size.