Study of electron traps in the thin interfacial oxide layer of Al-, Au- and Sn-n GaAs Schottky barriers by detrapping experiments

Electron traps in MIS-type Schottky barriers on n-GaAs were investigated by measuring the change of the flat-band voltage, due to detrapping, as a function of time. The trap depth and the capture cross section for a particular trap were obtained from the temperature dependence of the time constant for detrapping. It was found that the detrapping process in some cases is a two-state thermionic emission and tunneling process. For other trapping levels the results indicated clearly that the mechanism was different from the thermionic emission and tunneling process.     

The influence of a HF and an annealing treatment on the barrier height of p- and n-type Si MIS structures

In this paper, the influence of two pre-evaporation surface treatments on the electrical characteristics of n- and p-Si/Au, Cr and Ti MIS diodes are studied. A strong dependence of the barrier height on the pre-evaporation treatment is observed and is found to be independent of the metal work function. In order to explain this, it is suggested that the interfacial charges are strongly affected by the pre-evaporation treatment used.     

Ni/Pd/Si固相反应及NiSi热稳定性增强研究

研究了Ni/Pd双层薄膜在硅衬底上的硅化物形成过程.结果表明,加入Pd层后,退火形成Ni1-xPdxSi固熔体,该固熔体比NiSi的热稳定性好,使得NiSi向NiSi2的转变温度升高.加入Pd的量越多,NiSi2的成核温度越高,并用经典成核理论解释了该现象.     

Double threshold behaviour of I－V characteristics of CoSi2/Si Schottky contacts

The forward current－voltage (I－V) characteristics of polycrystalline CoSi₂/n-Si(100) Schottky contacts have been measured in a wide temperature range. At low temperatures (≤200K), a plateau-like section is observed in the I－V characteristics around 10^-4A·cm^-2. The current in the small bias region significantly exceeds that expected by the model based on thermionic emission (TE) and a Gaussian distribution of Schottky barrier height (SBH). Such a double threshold behaviour can be explained by the barrier height inhomogeneity, i.e. at low temperatures the current through some patches with low SBH dominates at small bias region. With increasing bias voltage, the Ohmic effect becomes important and the current through the whole junction area exceeds the patch current, thus resulting in a plateau-like section in the I－V curves at moderate bias. For the polycrystalline CoSi₂/Si contacts studied in this paper, the apparent ideality factor of the patch current is much larger than that calculated from the TE model taking the pinch-off effect into account. This suggests that the current flowing through these patches is of the tunnelling type, rather than the thermionic emission type. The experimental I－V characteristics can be fitted reasonably well in the whole temperature region using the model based on tunnelling and pinch-off.     

掺Pt对Si(100)上形成的NiSi薄膜应力的影响

利用在线应力测试技术表征了掺入Pt后对镍硅化物薄膜应力性质的影响.通过改变NiSi薄膜中Pt含量以及控制热处理的升温、降温速率实时测量了薄膜应力,发现在Si(100)衬底上生长的纯NiSi薄膜和纯PtSi薄膜的室温应力主要是热应力,且分别为775MPa和1.31GPa,而对于Ni1-xPtxSi合金硅化物薄膜,室温应力则随着Pt含量的增加而逐渐增大.应力随温度变化曲线的分析表明,Ni1-xPtxSi合金硅化物薄膜的应力驰豫温度随Pt含量的增加,从440℃(纯NiSi薄膜)升高到620℃(纯PtSi薄膜).应力驰豫温度的变化影响了最终室温时的应力值.     

A study of sputter-induced defects in magnetron-sputtered CoSi2 and TiSi2 Schottky barriers on n- and p-type GaP

Magnetron-sputtered CoSi₂ and TiSi₂ Schottky barriers on n- and p-type GaP were investigated. Their hitherto unknown barrier heights were determined to be 0.98 eV (for CoSi₂/n-GaP and CoSi₂/p-GaP), 0.91 eV (for TiSi₂/n-GaP), and 0.90 eV (for TiSi₂/p-GaP). It was found that magnetron-sputtering induced a compensated layer near the surface, both for n- and p-type GaP, with a thickness of about 0.05 m. As the dependence of the shift of the Mott-Schottky intercept with the V-axis on the substrate dopant concentration obeyed some specific law, we proposed that the defects are neutral complexes of dopant ions and sputter-induced native defects. These native defects were assumed to depend on the Fermi level position, namely the P_Ga antisite and the V_P vacancy for p-GaP and the V_Ga vacancy for n-GaP. The conversion between these defects occurs by nearest neighbour hopping of a phosphorus atom. The Schottky barrier heights obtained on p-GaP could be explained by Fermi level pinning at the surface due to the P_Ga defects. This could not be confirmed by n-GaP as the energy level position of the V_Ga was not available. The defects could be annealed out between 200° C and 300° C and the associated change of the Schottky barrier height corroborated the proposed model.On leave from the Université de Burundi, Faculté des Sciences, Bujumbura, Burundi     

Untersuchung der Frequenzabh?ngigkeit der Impedanz nahezu ideal polarisierbarer Halbleiterelektroden aus CdSe, CdS und TiO2

Ohne Zusammenfassung     

用弹道电子显微术研究Co-Ti-Si系统的退火温度对CoSi2/Si势垒不均匀性的影响

通过在硅(100)衬底上淀积的Co(3nm)/Ti(1nm)双金属层在不同退火温度下的固相反应,在硅衬底上制备了超薄外延CoSi2薄膜.在低温下,用弹道电子显微术(BEEM)及其谱线(BEES)测量了CoSi2/Si接触的局域肖特基势垒高度.对于800℃退火的CoSi2/Si接触,势垒高度的空间分布基本符合高斯分布,其峰值在599meV,标准偏差为21meV.而对于700℃退火样品,势垒高度分布很不均匀,局域的势垒高度值分布在152meV到870meV之间,这可归因于CoSi2薄膜本身的不均匀性.     

In situ X-ray diffraction study of thin film Ir/Si solid state reactions

The solid state reaction between a thin (30 nm) Ir film and different Si substrates (p-type Si(1 0 0), n- and p-type Si(1 1 1), silicon on insulator (SOI) and polycrystalline Si) was studied using a combination of in situ X-ray diffraction (XRD), in situ sheet resistance and laser light scattering measurements. No significant influence of either the dopants or the substrate orientation was detected as a phase formation sequence of IrSi, Ir₃Si₄,Ir₃Si₅ and IrSi₃ was found for all samples. The presence of a thin (<4 nm) amorphous IrSi film at room temperature and its subsequent crystallization could be deduced from the appearance of a broad semi-amorphous diffraction peak in the XRD spectrum around 400 °C. The results were verified using ex situ Rutherford Backscattering Spectroscopy, Scanning Electron Microscopy and 4-point probe measurements on quenched samples. The activation energy of the crystallization process and the silicide growth was determined using a Kissinger analysis on ramp anneals with different ramp rates. In addition, the influence of up to 25 volumetric % (20.5 atomic %) of Ir to the silicide formation in the Ni/Si system was studied on SOI and polycrystalline Si substrates. In the presence of Ir, the temperature range over which the low resistivity NiSi exists, is reduced both through an increase in formation temperature and an earlier consumption by the formation of NiSi₂. After the heat treatment, a continuous distribution of Ir throughout the NiSi₂ phase was detected using X-ray photoelectron spectroscopy depth profiling. A low sheet resistance of was maintained on both substrates up to 900 °C.     

Digital Predistortion for 5G Small Cell: GPU Implementation and RF Measurements

In this paper, we present a high data rate implementation of a digital predistortion (DPD) algorithm on a modern mobile multicore CPU containing an on-chip GPU. The proposed implementation is capable of running in real-time, thanks to the execution of the predistortion stage inside the GPU, and the execution of the learning stage on a separate CPU core. This configuration, combined with the low complexity DPD design, allows for more than 400 Msamples/s sample rates. This is sufficient for satisfying 5G new radio (NR) base station radio transmission specifications in the sub-6 GHz bands, where signal bandwidths up to 100 MHz are specified. The linearization performance is validated with RF measurements on two base station power amplifiers at 3.7 GHz, showing that the 5G NR downlink emission requirements are satisfied.