Microprocessor testability

As the level of microprocessor complexity increases to several hundred thousand transistors for a single-chip machine, it is becoming very difficult to test commercially available designs to the level of fault coverage desired by some customers. In order to achieve near 100-percent coverage of single stuck-at faults, future microprocessors must be designed with special testing features (designed for testability). The authors describe the testing problem for microprocessors, including the various methods of generating test sets and their application by the user. A survey of the testability features of some of today's commercially available microprocessors is presented. Suggestions for testability features for future-generation microprocessors are also discussed     

Statistical fault sampling

Computational requirements often discourage, or even prohibit, complete fault simulation of circuit designs having greater than 20000 single stuck-at faults. To circumvent this problem, statistical sampling methods have been proposed that provide fault coverage values within a small, predictable error range by simulating only a fraction of the circuit's total faults and using the result fault coverage value as an estimate of the fault coverage for the total circuit. As an introduction to the application of sampling methods to fault simulation of integrated circuits, the statistical theory behind these sampling methods and proposed augmentations of these methods for improving the precision of the sample fault coverage are presented. Various proposed sampling schemes are applied to example circuit designs, and the results are analyzed     

Design for testability and built-in self test: a review

A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point insertion, and scan methods are discussed. On-chip hardware for real-time test-pattern generation and data compression are investigated. Several of the DFT methods are then combined to form BIST hardware configurations. Built-in evaluation and self-test (BEST), autonomous test, scan with random inputs, built-in logic block observer (BILBO), partitioning with BEST, test-point insertion with on-chip control, and combined test-pattern generation and data compression (CTGC) are considered. An overview of each BIST scheme is offered     

A metric for estimating the fault-secure behavior of digitalcircuits

A new fault secure metric (FSM) for design analysis of digital circuits is presented; it can be applied at a very early stage of the design cycle. A set of FSM models is also presented; they calculate the FSM of a circuit directly from its structural attributes. The quantities used in these FSM models are measurable from circuit analysis, and directly depend on measurable attributes of the circuit; thus the subjectivity of the FSM is minimal. The FSM models are consistent, in that only the attribute input values change for a specific circuit application. Hence, the cost of obtaining a figure of merit depends only on the cost of determining the circuit's attributes. This consistency also lends itself to automation of attribute measurements and FSM calculations. The FSM can be used to evaluate the FSM of a design, as well as the relative FS performance of various circuit design techniques. A case study using a 2-rail encoded test circuit demonstrates the validity of the FSM. The FSM models directly depend on measurable attributes of the circuit, so that the subjectivity of the FSM is minimal, and they are consistent, in that only the attribute input values change for a specific circuit application. Hence, the cost of obtaining a figure of merit depends only on the cost of determining the circuit's attributes. This consistency lends itself to automation of attribute measurements and FSM calculations. The validity of the FSM has been demonstrated for a 2-rail test circuit design     

ITA: An algorithm for I DDQ testability analysis

This paper presents the I _DDQ Testability Analysis (ITA) algorithm for the estimation of a circuit design's leakage fault testability. The algorithm is based on the calculation of the probability of applying each of a set of essential vectors to each gate in the circuit. The essential vectors for each gate represent the minimal vector set that provides maximal leakage fault coverage.ITA assumes independence of circuit net values, except in the case of reconvergent fanout. Reconvergent fanout is identified by levelizing the circuit and propagating sets of labels from the primary inputs forward through the circuit, beginning with unique labels (integers) on each primary input. ITA evaluation of reconvergent fanout points then uses a backward implication procedure to calculate the essential vector probability values for the reconvergent gate, except in the case where backward implication is not deterministic.Results of an implementation of ITA are presented for a set of benchmark circuits, including a sample of the ISCAS '85 and '89 circuits.