A Continuous Time Auto-Zero Offset Compensated Switched Capacitor Integrator

A continous mode CMOS switched capacitor integrator with almost zero offset is presented. The offset is compensated using an auto-zero technique and proper circut elements have been used to attenuate disturbances due to charge injection and clock feedthrough. The circuit includes two parallel paths which operate alternately in order to integrate in one path while compensating the offset in the other path. The circuit is capable of removing the offset voltage and its integral, and many other spurious signals at the output. The designed integrator has an initial offset of about –250 V which raises to an amount of about –400 V after one second of integration.     

3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N

parylene-N is used as a dielectric layer to create ultra low-loss 3-D vertical interconnects and coplanar waveguide (CPW) transmission lines on a CMOS substrate. Insertion loss of 0.013 dB for a 3-D vertical interconnect through a 15-$mu$ m-thick parylene-N layer and 0.56 dB/mm for a 50- $Omega$ CPW line on the parylene-N layer (compared to 1.85 dB/mm on a standard CMOS substrate) are measured at 40 GHz. L-shaped, U-shaped, and T-junction CPW structures are also fabricated with underpasses that eliminate the discontinuities arisen from the slot-line mode and are characterized up to 40 GHz. A 3-D low-noise amplifier using these post-processed structures on a 0.13-$mu$ m CMOS technology is also presented along with the investigation of parasitic effects for accurate simulation of such a 3-D circuit. The 3-D circuit implementation reduces the attenuation per unit length of the transmission lines, while preserving the CMOS chip area (in this specific design) by approximately 25%. The 3-D amplifier measures a gain of 13 dB at 2 GHz with 3-dB bandwidth of 500 MHz, noise figure of 3.3 dB, and output 1-dB compression point of ${+}$ 4.6 dBm. Room-temperature processing, simple fabrication, low-loss performance, and compatibility with the CMOS process make this technology a suitable choice for future 3-D CMOS and BiCMOS monolithic microwave integrated circuit applications that currently suffer from high substrate loss and crosstalk.      

A new heuristic for resource-constrained project scheduling in stochastic networks using critical chain concept

This paper presents a newly developed resource-constrained project scheduling method in stochastic networks by merging the new and traditional resource management methods. In each project, the activities consume various types of resources with fixed capacities. The duration of each activity is a random variable with a given density function. Since the backward pass method is implemented for feeding-in resources. The problem is to determine the finish time of each activity instead of its start time. The objective of the presented model is defined as minimizing the multiplication of expected project duration and its variance. The values of activities finish times are determined at decision points when at least one activity is ready to be operated and there are available resources. If at a certain point of time, more than one activity is ready to be operated but available resources are lacking, a competition among ready activities is carried out in order to select the activities which must be operated first. This paper suggests a competition routine by implementing a policy to maximize the total contribution of selected activities in reducing the expected project duration and its variance. In this respect, a heuristic algorithm is developed and compared with the other existing methods.     

Reduced-Memory Direct Digital Frequency Synthesizer Using Parabolic Initial Guess

Based on the parabolic approximation, which was recently introduced by the authors, a new architecture for sine-output direct digital frequency synthesizers has been developed. Due to using this approximation, and also considering several memory-reduction techniques, the proposed architecture is so designed that needs only 728 bits read-only memory for mapping a 12-bit phase address to 10-bit sine amplitude. The synthesizer has also been implemented and the experimental results show its desired operation and performance.     

A Novel Ultrafine Needle (UN) for Innocuous and Efficient Subcutaneous Insulin Delivery

Subcutaneous (SC) insulin injection has been demonstrated to be the most effective method for treatment of diabetes mellitus but is conventionally performed by hypodermic needles, leading to poor management of diabetes because of the pain, needle phobia, and tissue trauma. Identification of a viable, safe, and pain‐free alternative method has been a longstanding challenge in modern health care. Here, the thermoplastic droplet stretching technique is developed to create an ultrahigh‐aspect‐ratio needle mold with simple microstructure control. The optimized ultrafine needle (UN) with 4 mm length, minimized 120 µm outer diameter, and 15° sharp bevel angle is formed via electroplating of a metallic layer on the surface of a needle mold with forcing sharp tip. This novel UN enables minimally invasive 4 mm skin insertion to deliver insulin in the targeted SC layer. The similar relative areas under the curves of insulin concentration within UN and 31G needle in vivo insulin administration indicate that UN can ensure stable insulin absorption for secure blood glucose management. Additionally, the proposed fabrication method may facilitate industrialization and commercialization of the UN, holding great promise for replacement of hypodermic needles and for improvement of quality of life among patients with diabetes.     

A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of C_gd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S₂₁), high reverse isolation (S₁₂)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply.     

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

Self-assembling of Prussian blue nanocubic particles on nanoporous glassy carbon and its use in the electrocatalytic reduction of hydrogen peroxide

In this paper, self-assembled Prussian blue nanocubic particles on nanoporous glassy carbon was developed. The morphology of the PBNP-modified porous glassy carbon was characterized by scanning electron microscopy. The PBNP-GCE-red film-modified electrode was used for the sensitive detection of hydrogen peroxide. The electrochemical behavior of the resulting sensor was investigated using cyclic voltammetry and chronoamperometry. The value of α, k _cat, and D was calculated as 0.35, 1.7 × 10⁵ cm³ mol^?1 s^?1, and 2.6 × 10^?5 cm² s^?1, respectively. The calibration curve for hydrogen peroxide determination was linear over 0–600 μM with a detection limit (S/N = 3) of 0.51 μM.