Noise and power reduction in filters through the use of adjustablebiasing

A technique that enables the variation of bias currents in a filter without causing disturbances at the output is presented. Thus, the bias current can be kept at the minimum value necessary for the total input signal being processed, reducing the noise and power consumption. To demonstrate this approach, a dynamically biased log-domain filter has been designed in a 0.25-μm BiCMOS technology. The chip occupies 0.52 mm². In its quiescent condition, the filter consumes 575 μW and has an output noise of 4.4 nA rms. Signal-to-noise ratio greater than 50 dB over 3 decades of input and total harmonic distortion less than 1% for inputs less than 2.5 mA peak are achieved. The bias can be varied to minimize noise and power consumption without disturbing the output     

Simplified technique for syllabic companding in log-domain filters

It is shown that when syllabic companding is applied to log-domain filters using dynamic biasing, their large signal linearity can be exploited to eliminate the state variable compensation circuit. Owing to its simplicity, the proposed technique has several advantages over previous approaches     

Automatic Tuning of Time Constants in Continuous-Time Delta–Sigma Modulators

We describe a digital technique for estimating and correcting time constant shifts in continuous-time delta-sigma modulators. The proposed method is based on the principle that the in-band gain and the out-of-band performance of a modulator are related. If the modulator output is denoted as v(n), we show that the variance of p(n)equivv(n)-v(n-1) is a good indicator of the modulator RC time constants. An alternative indicator, which is easier to implement in hardware is proposed. Simulation results demonstrating the effectiveness of the proposed techniques are given     

A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS

A 5.3-GHz low-voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D-flip-flop (DFF). An improved glitch-free phase switching architecture through the use of retimed multiplexer control signals is introduced. A high-speed low-voltage DFF circuit is given. The programmable divider fabricated in 0.25-μm technology occupies 0.09 mm²; it consumes 17.4 mA at 1.8 V and 26.8 mA at 2.2 V. Operation of 5.5 GHz with 300-mV_pk single-ended input is achieved with a 2.2-V supply. The residual phase noise at the output is -131 dBc/Hz at an offset of 1 kHz from the carrier while operating from a 5.5 GHz input     

Internally varying analog circuits minimize power dissipation

We review several techniques that make possible the dynamic variation of analog circuits internally, without affecting their input-output characteristics. Particular attention is paid to companding (dynamic gain scaling), dynamic impedance scaling, dynamic biasing, and dynamic structure variation. A mixture of more than one of these techniques is appropriate in some cases. We use filters as a specific example of dynamical analog circuits and place particular emphasis on avoiding or eliminating transients at the output of such circuits, which would normally occur due to such dynamic variations. By allowing for dynamic internal variations, the power dissipation of such circuits can be lowered and can be made to depend on how demanding the task at hand is. This allows for large savings of energy drain over time, thus making possible long battery life in portable equipment.     

A Power Optimized Continuous-Time ∆Σ ADC for Audio Applications

We present design considerations for low-power continuous-time modulators. Circuit design details and measurement results for a 15 bit audio modulator are given. The converter, designed in a 0.18 mum CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 muW from a 1.8 V supply. It features a third-order active-RC loop filter, a very low-power 4-bit flash quantizer, and an efficient excess-delay compensation scheme to reduce power dissipation.