Critical evaluation of SOI design guidelines

Design guidelines for static and domino silicon-on-insulator (SOI) CMOS circuits are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-silicon. Most published design fixes for eliminating parasitic bipolar induced upset are shown to aggravate the charge sharing problem. A new and improved predischarge method for enhancing the noise tolerance of SOI domino circuits is thus proposed . The topic of multiple output domino logic in SOI technology is addressed for the first time. Multiple output domino logic is shown to be more prone to bipolar leakage induced upset than regular domino. Many of the design practices used to alleviate bipolar leakage in regular domino are no longer valid due to the multiple output domino logic's inherent design requirements. A novel SOI-specific multiple output domino logic, particularly suitable for adder designs, is introduced to minimize the bipolar leakage risk.     

Polynomial time approximation schemes and parameterized complexity

In this paper, we study the relationship between the approximability and the parameterized complexity of NP optimization problems. We introduce a notion of polynomial fixed-parameter tractability and prove that, under a very general constraint, an NP optimization problem has a fully polynomial time approximation scheme if and only if the problem is polynomial fixed-parameter tractable. By enforcing a constraint of planarity on the W-hierarchy studied in parameterized complexity theory, we obtain a class of NP optimization problems, the planar W-hierarchy, and prove that all problems in this class have efficient polynomial time approximation schemes (EPTAS). The planar W-hierarchy seems to contain most of the known EPTAS problems, and is significantly different from the class introduced by Khanna and Motwani in their efforts in characterizing optimization problems with polynomial time approximation schemes.     

On the stretch factor of Delaunay triangulations of points in convex position

Let S be a finite set of points in the Euclidean plane. Let G be a geometric graph in the plane whose point set is S. The stretch factor of G is the maximum ratio, among all points p and q in S, of the length of the shortest path from p to q in G over the Euclidean distance |pq|. Keil and Gutwin in 1989 [11] proved that the stretch factor of the Delaunay triangulation of a set of points S in the plane is at most 2π/(3cos(π/6))≈2.42. Improving on this upper bound remains an intriguing open problem in computational geometry.In this paper we consider the special case when the points in S are in convex position. We prove that in this case the stretch factor of the Delaunay triangulation of S is at most ρ=2.33.     

Secure MIMO D2D communication based on a lightweight and robust PLS cipher scheme

Wireless Networks - The Multiple-Input Multiple-Output (MIMO) technology is one of the key enablers of the 5G system. This technology allows the concurrent transmission of data using multiple...     

Conductance Photoswitching of Metal–Organic Frameworks with Embedded Spiropyran

Conductive metal–organic frameworks (MOFs) as well as smart, stimuli‐responsive MOF materials have attracted considerable attention with respect to advanced applications in energy harvesting and storage as well as in signal processing. Here, the conductance of MOF films of type UiO‐67 with embedded photoswitchable nitro‐substituted spiropyrans was investigated. Under UV irradiation, the spiropyran (SP) reversibly isomerizes to the open merocyanine (MC) form, a zwitterionic molecule with an extended conjugated π‐system. The light‐induced SP–MC isomerization allows for remote control over the conductance of the SP@UiO‐67 MOF film, and the conductance can be increased by one order of magnitude. This research has the potential to contribute to the development of a new generation of photoelectronic devices based on smart hybrid materials.     

Design Considerations for PD/SOI SRAM: Impact of Gate Leakage and Threshold Voltage Variation

We present a critical study of the impact of gate tunneling currents on the yield of 65-nm partially depleted/silicon-on-insulator (PD/SOI) SRAM designs. A new gate leakage monitor structure is developed to obtain device-specific gate leakage characteristics of the SRAM cells. This allows us to explore the design space accurately with reliable process information at an early stage. By relying on supply voltage-dependent analysis, it is shown that the gate-leakage impact on the cell yield can be nonmonotonic and substantial even for nondefective devices. It is also shown that design optimizations such as increased operating voltages or shorter hierarchical bitline architecture can help alleviate the gate-leakage impact on yield. Mixture importance sampling is used to estimate yield in terms of cell writability and stability. Threshold voltage variations to model random fluctuation effects are extrapolated from hardware results.     

Optimized joint cell planning and BS on/off switching for LTE networks

Energy is becoming a main concern nowadays due to the increasing demands on natural energy resources. Base stations (BSs) consume up to 80% of the total energy expenditure in a cellular network. In this paper, we propose and evaluate a green radio network planning approach by jointly optimizing the number of active BSs and the BS on/off switching patterns based on the changing traffic conditions in the network in an effort to reduce the total energy consumption of the BSs. The problem is formulated as an integer optimization problem, which proves to be NP‐complete, and thus it can be efficiently solved for small to medium network sizes. For large network sizes, we propose a heuristic solution with close to optimal performance because the optimal solution becomes computationally complex. Planning is performed based on two approaches: a reactive and a proactive approach. In the proactive approach, planning will be performed starting with the lowest traffic demand until reaching the highest traffic demand, whereas in the reactive approach, the reverse way is considered. Performance results are presented for various case studies and are complemented by testing the proposed approaches using commercial radio network planning tools. Results demonstrate considerable energy savings reaching up to 40% through dynamic adaptation of the number of simultaneously active BSs. Copyright © 2015 John Wiley & Sons, Ltd.     

Local Construction of Near-Optimal Power Spanners for Wireless Ad Hoc Networks

We present a local distributed algorithm that, given a wireless ad hoc network modeled as a unit disk graph U in the plane, constructs a planar power spanner of U whose degree is bounded by k and whose stretch factor is bounded by 1 + (2sin{frac{pi}{k}})^{p}, where k geq 10 is an integer parameter and p in [2, 5] is the power exponent constant. For the same degree bound k, the stretch factor of our algorithm significantly improves the previous best bounds by Song et al. We show that this bound is near-optimal by proving that the slightly smaller stretch factor of 1 + (2sin{frac{pi}{k + 1}})^{p} is unattainable for the same degree bound k. In contrast to previous algorithms for the problem, the presented algorithm is local. As a consequence, the algorithm is highly scalable and robust. Finally, while the algorithm is efficient and easy to implement in practice, it relies on deep insights on the geometry of unit disk graphs and novel techniques that are of independent interest.