Spatial retardation of carrier heating in scaled 0.1-μmn-MOSFET's using Monte Carlo simulations

A comprehensive Monte Carlo simulator is employed to investigate nonlocal carrier transport in 0.1 μm n-MOSFET's under low-voltage stress. Specifically, the role of electron-electron (e-e) interactions on hot electron injection is explored for two emerging device designs biased at a drain voltage V_d considerably less than the Si/SiO₂ injection barrier height φ_b. Simulation of both devices reveal that 1) although qV_d<φ_b, carriers can obtain energies greater than φ_b, and 2) the peak for electron injection is displaced approximately 20 nm beyond the peak in the parallel channel electric field. These phenomena constitute a spatial retardation of carrier heating that is strongly influenced by e-e interactions near the drain edge. (Virtually no injection is observed in our simulations when e-e scattering is not considered.) Simulations also show that an aggressive design based on larger dopant atoms, steeper doping gradients, and a self-aligned junction counter-doping process produces a higher peak in the channel electric field, a hotter carrier energy distribution, and a greater total electron injection rate into the oxide when compared to a more conventionally-doped design. The impact of spatially retarded carrier heating on hot-electron-induced device degradation is further examined by coupling an interface state distribution obtained from Monte Carlo simulations with a drift-diffusion simulator. Because of retarded carrier heating, the interface states are mainly generated further over the drain region where interface charge produces minimal degradation. Thus, surprisingly, both 0.1 μm n-MOSFET designs exhibit comparable drain current degradation rates     

Comparative analysis of hot electron injection and induced devicedegradation in scaled 0.1 μm SOI n-MOSFETs using Monte Carlosimulation

A self-consistent Monte Carlo (MC) simulator is employed to investigate and compare hot electron phenomena in three competing design strategies for 0.1 μm SOI n-MOSFETs operating under low voltage conditions, i.e., V_d considerably less than the Si-SiO₂ injection barrier height φ_b. Simulations of these designs reveal that non-local carrier transport effects and two-dimensional current how play a significant role in determining the relative rate and location of hot electron injection into both the front and back oxides. Specifically, simulations indicate that electron-electron interactions near the drain edge are a main source of electron energies exceeding φ_b. The hot electron injection distributions are then coupled with an empirical model to generate interface state distributions at both the front and back oxide interfaces. These interface states are incorporated into a drift-diffusion simulator to examine relative hot-electron-induced device degradation for the three 0.1 μm SOI designs. Simulations suggest that both the Si layer thickness and doping distribution affect device sensitivity to hot-electron-induced interface states. In particular, the simulations show that a decrease in the channel doping results in increased sensitivity to back oxide charge. In the comparison of the heavily-doped designs, the design with a thinner T_Si experiences significantly more hot-electron-induced oxide damage in the back oxide and more degradation from the charged states at the back interface     

Ensemble Monte Carlo study of interface-state generation inlow-voltage scaled silicon MOS devices

An ensemble Monte Carlo (MC) model coupled with an interface-state generation model was employed to predict the quantity and lateral distribution of hot-electron-induced interface states in scaled silicon MOSFETs. Constant field and more generalized scaling methods were used as the basis to simulate devices with 0.33-, 0.20-, and 0.12-μm channel lengths. The dependencies of interface-state generation on applied bias and electric field profiles were investigated. Hot-electron injection and interface-state density profiles were simulated at biases as low as 1.44 V (i.e., lower than the 3.1 V potential barrier at the Si/SiO₂ interface). These simulations demonstrate that “lucky electron” and/or electron temperature models are no longer accurate for predicting hot-electron effects in such regimes. Electron-electron scattering is shown to be a critical consideration for simulation of hot-electron injection at low drain to source bias voltages, where local interfacial barrier heights are greater than the energy gained by an electron from the applied electric field. Simulations indicate that a scaled decrease in the channel length of a device may be accompanied by an increase in the lateral electric field without incurring a penalty for higher hot-electron degradation. It is also shown that conventional hot-electron stressing using accelerated stress bias conditions may continue to be valuable for predicting the reliability of device designs scaled to 0.1-μm channel lengths     

Effects of silicon layer properties on device reliability for0.1-μm SOI n-MOSFET design strategies

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10¹⁶ cm^-3) channel and 2) a heavily-doped (10¹⁸ cm^-3) channel. For each design, the silicon layer thicknesses (T_Si) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO₂ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T_Si results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead