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1.
Clifford Henry Taubes 《Communications in Mathematical Physics》1989,122(3):455-526
A proof is given of Witten's conjectures for the rigidity of the index of the Dirac-Ramond operator on the loop space of a spin manifold which admits anS
1 symmetry.Research supported in part by the National Science Foundation 相似文献
2.
Henry P. McKean 《纯数学与应用数学通讯》2003,56(5):638-680
3.
Justina Grabowska Karuna Kar Nanda R.T. Rajendra Kumar J.P. Mosnier M.O. Henry Simon B. Newcomb Patrick McNally Lisa OReilly Xu Lu Enda McGlynn 《Superlattices and Microstructures》2007,42(1-6):327
Self-organized ZnAl2O4 nanostructures with the appearance (in SEM) of high aspect ratio horizontal nanowires are grown on uncatalysed c-sapphire by vapour phase transport. The nanostructures grow as three equivalent crystallographic variants on c-sapphire. Raman and cathodoluminescence spectroscopy confirm that the nanostructures are not ZnO and TEM shows that they are the cubic spinel, zinc aluminate, ZnAl2O4, formed by the reaction of Zn and O with the sapphire substrate. 相似文献
4.
Add-drop filters are demonstrated using silica-on-silicon optical waveguide technology. This device consists of a full directional coupler subdivided by Mach-Zehnder sections. Tapering of the coupling coefficients is experimentally shown to dramatically reduce the filters' sidelobes. Only one photolithographic step is required using the silica planar waveguide technology, yielding accurate wavelength control of the filters. Excellent agreement between measurement and design was achieved 相似文献
5.
Efficiency improvement of near-ultraviolet InGaN LEDs using patterned sapphire substrates 总被引:1,自引:0,他引:1
Woei-Kai Wang Dong-Sing Wuu Lin S.-H. Han P. Horng R.-H. Ta-Cheng Hsu Huo D.T.-C. Ming-Jiunn Jou Yuan-Hsin Yu Lin A. 《Quantum Electronics, IEEE Journal of》2005,41(11):1403-1409
The use of conventional and patterned sapphire substrates (PSSs) to fabricate InGaN-based near-ultraviolet (410 nm) light-emitting diodes (LEDs) was demonstrated. The PSS was prepared using a periodic hole pattern (diameter: 3 /spl mu/m; spacing: 3 /spl mu/m) on the (0001) sapphire with different etching depths. From transmission-electron-microscopy and etch-pit-density studies, the PSS with an optimum pattern depth (D/sub h/=1.5 /spl mu/m) was confirmed to be an efficient way to reduce the thread dislocations in the GaN microstructure. It was found that the output power increased from 8.6 to 10.4 mW, corresponding to about 29% increases in the external quantum efficiency. However, the internal quantum efficiency (@ 20 mA) was about 36% and 38% for the conventional and PSS LEDs, respectively. The achieved improvement of the output power is not only due to the improvement of the internal quantum efficiency upon decreasing the dislocation density, but also due to the enhancement of the extraction efficiency using the PSS. Finally, better long-time reliability of the PSS LED performance was observed. 相似文献
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Fractional-sample delay in discrete-time systems is often provided by special FIR filters which are asymmetric about mid-sequence. Here we preserve the appeal of sine-sequence fractional delayers (simplicity and single-parameter delay tuning) by devising a two-term raised-cosine window which delivers fractional-delay filters comparable to the best obtainable by highly regarded optimisation approaches 相似文献
9.
Linda Kwai-Lin Lau Rajeev Jain Henry Samueli Henry T. Nicholas III Etan G. Cohen 《The Journal of VLSI Signal Processing》1992,4(2-3):213-226
This paper presents a functional compiler for the automatic design of Direct Digital Frequency Synthesizer (DDFS) integrated circuits (ICs) using a ROM based table look-up architecture. The compiler allows the user to specify high-level specifications such as the acceptable spurious response and it generates the IC architecture, floorplan, and layout. To construct the layout for different specifications, a library of parameterized macrocells has been developed in 1.2 m CMOS technology.A test chip with a quadrature DDFS module has been generated, using the compiler, and fabricated. The chip has two input signals: one is for frequency control while the other is for phase initialization. Input and output word lengths are 16 bits and 6 bits respectively. The chip complexity is approximately 12,000 transistors (DDFS core) and the die size is 4.8×2.9mm
2. A maximum sample rate of 80 MHz has been attained implying a maximum sine (cosine) output frequency of 40 MHz and a frequency resolution of 1.22 kHz. The maximum spurious level measured is –46 dB. 相似文献
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