A CMOS differential buffer amplifier with accurate gain andclipping control

A CMOS fully differential buffer amplifier with accurate gain and clipping control is presented. The gain is made variable by controlling the amount of the feedback around the power amplifier by means of an additional gain control loop. A new clipping technique is used to control the clipping level of the amplifier. The amplifier is realized in a 1.2 μm CMOS process with a single 5 V power supply. Measurements confirm the presented techniques     

A 4/7 kHz audio bandwidth selectable digital phone interface (DPI)chip with on-chip analog functions and modem

The Digital Phone Interface (DPI) is designed for a new generation of digital telephone terminals for private exchanges, This circuit gives a total solution for all telephone functions, thereby including DSP functions, voice coding/decoding and analog front end, signal generators for DTMF and ringing, a modem for data transfer between terminal and exchange and a multitude of interfaces to communicate to the external world. Besides the normal earpiece micro and speaker, handsfree operation is available by using a selectable input low-noise microphone amplifier and an additional 50 Ω mWLS driver. For the handsfree operation, a digital AGC and anti-oscillation (anti-larsen) function is implemented. The line modem generates a modified RTZ (WAL2) code and is able to cover distances up to 1.5 km. In addition, the component is extensible with external signal processing modules (echo cancelling) and is also able to transfer a 7 kHz speech bandwidth. The device is a mixed analog/digital design produced in a 1.2 μm CMOS technology on 46 mm ² die area and consumes 200 mW     

A total solution for a 9600-b/s modem transmitter chip

A single-chip analog transmitter (TX chip) for a V29-V32 9600-b/s modem has been implemented in a 3-μm CMOS n-well process. A high level of integration permits a low-cost, high-performance modem to be built. The TX chip is composed of analog, switched capacitor, and digital circuits. The important functions realized are the phase-point generator, the cosine roll-off low-pass filter, the modulator, and the programmable equalization filters. The chip occupies 29 mm² and dissipates 300 mW     

A general purpose design-for-test methodology at the analog-digital boundary of mixed-signal VLSI

A general-purpose modular-based scan chain between the analog-digital boundary of a mixed analog/digital design is proposed. This general-purpose Design-For-Test methodology is oriented towards the test of the mixed-signal modules within the design. Implementing this structure improves the controllability and observability of these modules and the reusability of the test software at a minimum cost.     

A four-channel digital signal processor in 1.2-μm CMOS withon-chip D/A and A/D conversion serving four speech channels in anew-generation subscriber line circuit

The major component for a new-generation line circuit was designed and fabricated in a 1.2-μm CMOS technology. The circuit includes digital signal processing of receive (RX) and transmit (TX) signals as well as the analog front end of four subscriber lines to a PCM (pulse code modulation) digital exchange. The device operates on a single 5-V power supply. The four-channel digital signal-processor including the analog front ends is fabricated on a 40-mm² 1.2-μm CMOS die area. The DSP functions, the RX and TX filters, the decimator, the interpolator, and the A/μ-law transcoder are included as independent data paths, one for the TX and RX filters, one for the decimator, and another for the interpolator, the digital sigma-delta modulator, and the transcoder. The on-chip analog front end contains a notch filter to cancel the 12/16-kHz payphone signal, a switched-capacitor PDM A/D and D/A converter, and smoothing filters. On the first measured samples, the signal-to-distortion ratio is measured to be 33 dB at -45 dBmo for -7 dB gain setting     

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOStechnologies

In this paper, the performance and reliability characteristics of the 0.35 μm/0.25 μm High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 μm CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 μs) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125°C. Furthermore, the cell has been scaled to a 0.25 μm version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V     

The Second International Nurse Rostering Competition

Annals of Operations Research - This paper reports on the Second International Nurse Rostering Competition (INRC-II). Its contributions are (1) a new problem formulation which, differently from...     

Wireless telecom silicon integration: analog design for radio,baseband and speech spectrum

The application today, pushing analog design for CMOS and RFbipolar into new frontiers is definitely the mobile radio telephony. New telecom systems like GSM, PCN, DECT, DCS, Wireless in the loop ... are all developing very rapidly and will enable us very soon to organise a complete telephone network with full coverage for your car, as well as in your kitchen and on your office desk. In Europe the major telecom companies have worked together to establish one common standard for cellular mobile radio communications at 900 MHz. Similar things are happening for other wireless personal communication systems. Basically the cellular radio telephone, the wireless PABX and the wireless SLIC are bringing the same challenges to analog circuit design: maximum integration of the basic radio functions into 1 or 2 silicon chips, CMOS, Bipolar or BiCMOS or GaAs. The analog circuit designer for radio telephone applications will need all the state of the art analog design knowhow available today, from RFmixers and GHz range low noise amplifiers and local oscillator synthesizers over base band 100 kHz CMOS analog to low frequency speech analog to digital conversion. And for all these circuits the message is: minimum power consumption for battery autonomy, minimum silicon area for maximum functional integration per die to obtain a small, low cost pocket size radio telephone.     

A flash memory technology with quasi-virtual ground array forlow-cost embedded applications

In this paper, the 0.35-μm implementation of a 1-Mb embedded flash memory circuit, based on a split-gate concept, is presented. This concept provides an excellent solution for embedded applications, thanks to the very limited number of processing steps that are needed on top of a baseline CMOS process. Nevertheless, a high performance memory cell is obtained that operates with moderate voltages only. Furthermore, the source-side injection (SSI) mechanism used for cell programming exhibits a very narrow threshold voltage (V_t) distribution, which is maintained even after 1 million program/erase cycles. Because of this tight distribution and the inherent overerase immunity, no additional verification circuitry is needed, which greatly simplifies the decoder design and minimizes the memory footprint. Finally, the memory cell is placed in a quasi-virtual ground array (QVGA) configuration, resulting in a compact memory area with only three quarters of a contact per cell, whereas most arrays require at least a full contact per cell or more