A 16-Mb MRAM featuring bootstrapped write drivers

A 16-Mb magnetic random access memory (MRAM) is demonstrated in 0.18-/spl mu/m three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42/spl mu/m/sup 2/ 1-transistor 1-magnetic tunnel junction (1T1MTJ) cell, measures 79 mm/sup 2/ and features a /spl times/16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented.     

A high-speed 128-kb MRAM core for future universal memory applications

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.     

A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control

A 2-Mbit CBRAM (Conductive Bridging Random Access Memory) core has been developed utilizing a 90 nm, VDD=1.5 V process technology. The presented design uses an 8F² (0.0648 mum²) 1T1CBJ (1-Transistor/1-Conductive Bridging Junction) cell and introduces a fast feedback regulated CBJ read voltage and a novel program charge control using dummy cell bleeder devices. Random read/write cycle times les50ns are demonstrated     

Memories of tomorrow

With the promise of nonvolatility, practically infinite write endurance, and short read and write times, magnetic tunnel junction magnetic random access memory could become a future mainstream memory technology.     

A 1-Kbit EEPROM in SIMOX technology for high-temperatureapplications up to 250°C

A 1-Kbit high-temperature EEPROM memory module has been developed in a 1.6-μm thin-film SIMOX technology. The memory array is based on single-poly EEPROM cells, which are erased and programmed by Fowler-Nordheim tunneling. Operation at elevated temperatures is achieved by a special array design, suitable for elimination of cell-disturb problems caused by temperature-induced leakage currents of the select transistors. High-voltage switching is done without PMOS transistors in order to avoid leakage currents due to the backgate effect. The memory module is designed for 5-V only operation and offers an access time of 260 ns at an operating temperature of 250°C. At 250°C, data retention of 3000 h and an endurance of 10000 erase/program cycles has been achieved. The area of the 1-Kbit memory module is 0.89×2.71 mm²     

A single-poly EEPROM cell in SIMOX technology for high-temperatureapplications up to 250°C

A thin-film SIMOX technology has been used for fabrication of a single-polysilicon EEPROM cell suitable for high-temperature applications. The two transistor cell is composed of a select transistor and a floating gate transistor with 10 nm tunnel oxide. The EEPROM process extension requires only a few steps suitable for embedded memory applications with low cost and turn around time. Endurance and data retention characteristics of the SIMOX EEPROM cell are presented for a temperature of 250°C. The problem of temperature induced leakage currents in the select transistor at elevated temperatures is investigated