Evaluating power consumption of parameterized cache and busarchitectures in system-on-a-chip designs

Architectures with parameterizable cache and bus can support large tradeoffs between performance and power. We provide simulation data showing the large tradeoffs by such an architecture for several applications and demonstrating that the cache and bus should be configured simultaneously to find the optimal solutions. Furthermore, we describe analytical techniques for speeding up the cache/bus power and performance evaluation by several orders of magnitude over simulation, while maintaining sufficient accuracy with respect to simulation-based approaches     

System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip

In this work, we provide a technique for efficiently exploring the power/performance design space of a parameterized system-on-chip (SOC) architecture to find all Pareto-optimal configurations. These Pareto-optimal configurations will represent the range of power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application that is mapped on the SOC architecture. Our approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. We have successfully applied our technique to explore Pareto-optimal configurations of our SOC architecture for a number of applications.     

Converting the UK calculation of road traffic noise (CORTN) to a model capable of calculating LAeq,1h for the Tehran’s roads

This paper describes the methodology through which the UK calculation of road traffic noise (CORTN) has been converted to the algorithms that are able to calculate hourly A-weighted equivalent sound pressure level (L_Aeq,1h) for the Tehran’s roads. The methodology adopts two different approaches to model calibration and performance test through the holdout validation method on the basis of the database including 52 samples taken from 52 sampling stations located alongside 5 roads of Tehran at distances less than 4 m from the nearside carriageway edge. As to the CORTN manual the distances less than 4 m are considered to be equal to 4 m. In the first approach the model is calibrated through carrying out nonlinear regression parameter estimation using 50% of samples to replace the basic noise level parameters with the new ones that are presumably able to satisfy the objective of the study with an acceptable fitness of the model. In the second approach the model calibration is carried out on the basis of 30 measurements taken from 2 roads. In the next step the other subsets of samples are introduced into the calibrated equations to conduct the performance test. Non parametric goodness of fit tests, i.e. two related samples Wilcoxon and two independent samples Kolmogorov-Smirnov, respectively conducted for the calibration and the performance test steps; indicate satisfactory results for both approaches.     

Mathematical, statistical and neural models capable of predicting LA,max for the Tehran-Karaj express train

This paper presents mathematical logarithmic, statistical linear regression, and neural models capable of predicting maximum A-weighed noise level (L_A,max) for the Tehran-Karaj express train. The models have been developed upon the basis of the measurements from sampling locations at distances of 25 m, 45 m, and 65 m from the centreline of the track and at a height of 1.5 m. In the next step, the predictive capability of the models have been tested on the data associated with the sampling locations, situated, respectively at distances of 35 and 55 m from the centreline of the track at a height of 1.5 m. The non-parametric tests i.e. two-related samples Wilcoxon, and two-independent samples Kolmogorov-Smirnov, carried out, respectively for training and testing steps, indicate satisfactory results. In the final step the non-parametric k-related samples Friedman test detects no significant differences amongst the absolute testing set error of the models.     

Instruction-based system-level power evaluation of system-on-a-chip peripheral cores

Various core-based power evaluation approaches for microprocessors, caches, memories and buses have been proposed in the past. We propose a new power evaluation technique that is targeted toward peripheral cores. Our approach is the first to combine for peripherals both gate-level-obtained power data with a system-level simulation model written in an object-oriented language. Our approach decomposes peripheral functionality into so-called instructions. The approach can be applied with three increasingly fast methods: system simulation, trace simulation or trace analysis. We show that our models are sufficiently accurate in order to make power-related system-level design decisions but at a computation time that is orders of magnitude faster than a gate-level simulation.     

Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms

System-on-a-chip platform manufacturers are increasingly adding configurable features that provide power and performance flexibility, in order to increase a platform's applicability to a variety of embedded computing systems. We illustrate the energy benefits of combining the configurable features of voltage scaling and cache way shutdown in a single platform. We describe methods to assist a designer to tune such a platform to a particular software task and to particular energy optimization criteria.     

Optimizing control flow in loops using interval and dependence analysis

We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for significant performance increase. The transformation technique optimizes loops containing nested conditional blocks. Specifically, the transformation takes advantage of the fact that the Boolean value of the conditional expression, determining the true/false paths, can be statically analyzed using a novel interval analysis technique that can evaluate conditional expressions in the general polynomial form. Results from interval analysis combined with loop dependency information is used to partition the iteration space of the nested loop. In such cases, the loop nest is decomposed such as to eliminate the conditional test, thus substantially reducing the execution time. Our technique completely eliminates the conditional from the loops (unlike previous techniques) thus further facilitating the application of other optimizations and improving the overall speedup. Applying the proposed transformation technique on loop kernels taken from Mediabench, SPEC-2000, mpeg4, qsdpcm and gimp, on average we measured a 2.34X speedup when running on a UltraSPARC processor, a 2.92X speedup when running on an Intel Core Duo processor, a 2.44X speedup when running on a PowerPC G5 processor and a 2.04X speedup when running on an ARM9 processor. Performance improvement, taking the entire application into account, was also promising: for 3 selected applications (mpeg-enc, mpeg-dec and qsdpcm) we measured 15% speedup on best case (5% on average) for the whole application.