Tri-Gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap

A tri-gate bulk MOSFET design utilizing a low-aspect-ratio channel is proposed to provide an evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations indicate that this design offers the advantages of a multi-gate FET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).     

Deposition thickness based high-throughput nano-imprint template

International Technology Roadmap for Semiconductors 2003 projected nano-imprint lithography has the potential of high throughput, sub-20 nm resolution, and low cost [S.Y. Chou, P.R. Krauss, P.J. Renstrom, Appl. Phys. Lett. 67 (1995) 3144; Science 272 (1996) 85, J.A. Rogers, C. Mirkin, Mater. Res. Bull. 26 (2001)]. For nano-imprint lithography, a template with 1X resolution is required. The existing industrial infrastructure for supporting deep ultra violet 4X photo masks by e-beam and/or a laser beam scanning writer does not offer pitch (center-to-center distance of an array of patterned lines) less than ∼60 nm [<http://public.itrs.net/2003ITRS>]. For nano-imprint lithography to be accepted across the industry, a reproducible simple fabrication process to make a high resolution, single emboss template is essential [L. Jay Guo, J. Phys. D: Appl. Phys. 37 (2004) R123-R141]. Here we show, a general fabrication method and fabricated nano-imprint templates with sub-15 nm template line width and 10 nm pitch length through out the entire 200 mm wafer, varying the deposition thickness of multiple alternate films, using atomic layer deposition. Although multilayer nano-imprint templates and their exciting use have been demonstrated, [W.J. Dauksher et al., J. Vac. Sci. Technol. B 22 (2004) 3306, B. Heidari, et al., The 49th international conference on electron, ion and photon beam technology and nanofabrication, Orlando, Florida, 2005, William M. Tong, et al., Proc. SPIE 5751 (2005) 46-55, N.A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P.M. Petroff, J.R. Heath, Science 300 (2003) 112] such a small pitch was not shown and either complex lattice mismatch-based epitaxially grown films or unconventional etch chemistry was used. The bare necessity was a simple and economical fabrication process for a high throughput nano-imprint template. In that context, we have developed a template fabrication process using classical micro-fabrication techniques. Successful use of these techniques made the template fabrication process simple, economical, and expedient. Also a novel technique to provide flexible and accurate alignment for nanowire patterning has been described. In this technique, nanowire patterning is accomplished on the entire wafer with a single impression. Industry level batch-fabrication of our scheme illustrates its reproducibility and manufacturability. We anticipate, this simple, economical and time saving technique will help researchers and developers to perform their experiment on nano-scale feature patterned substrates easily and conveniently.     

设计的复杂性呼唤系统级设计

以自然语言编写的产品规范的含糊其辞，常常会带来设计缺陷，而这种缺陷直到较晚阶段才会被发现，从而使解决方案变得更加昂贵。     

在设计过程早期发现并解决问题

要想保持印制电路板信号完整性,就应该采用能使印制线阻抗得到精确匹配的层间互连(通孔)这样一种独特方法.     

高性能低价位的印制电路板设计工具

台式印制电路板CAE工具具备各种功能。在当今经济紧缩的年代,这种低价位工具更显出它的优越性和价值。     

导线延迟与SVP技术

SVP(硅虚拟原型)是新世纪的产物.直到三年以前,延迟一直是信号传播时间中的最重要部分.因此,工程师们可以非常精确地估计出互连延迟,而不必在布局布线问题上花太多注意力就可以完成电路设计.     

第三方IP：SOC设计的一种不稳固基础

商用模块有助于设计师实现开发进度和成本目标，但风险很大。     

Parameter variation in low-quartz between 94 and 298K

The structure of low quartz has been refined at 94, 115, 150, 190, 240 and 298K using Mo Kα intensities up to 2θ = 90° with residuals around 1.25%. The major structural change from 94 to 298K is an increase of the SiOSi angle from 142.69(4) to 143.65(5) corresponding to a rotation by ～0.8° of a rigid SiO₄ tetrahedron around the crystallographic 2-axis through its central Si. The orientations of the principal axes of vibration of Si and O do not change significantly with temperature. The temperature dependence of the mean-square displacement of O along its principal axes follows the Debye formula of thermal motion quite well, while for Si the experimental slopes are significantly less than their calculated values.