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Flannagan S.T. Pelley P.H. Herr N. Engles B.E. Feng T. Nogle S.G. Eagan J.W. Dunnigan R.J. Day L.J. Kung R.I. 《Solid-State Circuits, IEEE Journal of》1990,25(5):1047-1056
SRAMs (static random-access memory) with a 64 K×4 and 256 K×1 structure and with 8-ns access time have been developed on a 1.0-μm CMOS process. Circuits are designed with source-coupling techniques to achieve high speed with small signal swings, using only CMOS devices. A metal option permits selection of the 64 K×4 or 256 K×1 configuration. The same core architecture has also been used to generate ×8 and ×9 designs. An output-enable (OE) version achieves 3-ns response time. As system speeds have recently increased toward 100-MHz operation, the need for address transition detection (ATD) has diminished as a means for improving the SRAM speed/power ratio. This trend in SRAM design stems mainly from the fact that AC current becomes the most significant fraction of the total current. Accordingly, the design described here employs a purely static path through the entire SRAM, with no requirement of ATD at any point. The resulting DC current is countered with a combined strategy of array subdivision, small-signal techniques, and active preamplification at key points in the data path 相似文献
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T. B. Flannagan 《Archive for Mathematical Logic》1980,20(3-4):173-180
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